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https://github.com/UzixLS/TSConf_MiST.git
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31 lines
805 B
Verilog
31 lines
805 B
Verilog
`timescale 1ns/100ps
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`ifdef MODEL_TECH
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`define SIMULATE
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`endif
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//`define DRAMMEM_VERBOSE
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//`define FETCH_VERBOSE
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// `define FREE_IORQ // for non-blocked by internal ports !IORQ
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// `define IDE_HDD // for IDE HDD
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`define IDE_VDAC // for VideoDAC instead of IDE
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// `define IDE_VDAC2 // for VideoDAC2 instead of IDE
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`define XTR_FEAT // extra features, in only IDEless version
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// `define SD_CARD2 // for second SD Card
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// `define AUTO_INT // auto-incremented Frame Interrpt
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// `define FDR // FDD Ripper version (use with DISABLE_TSU)
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// `define DISABLE_TSU // disable TSU
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// `define PENT_312 // for Pentagon 71680 tacts emulation with 312 video lines
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`define KEMPSTON_8BIT // 8-bit enhanced Kempston Joystick interface
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`define ENABLE_60HZ
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