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https://github.com/UzixLS/TSConf_MiST.git
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114 lines
2.9 KiB
Verilog
114 lines
2.9 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2016
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Based on information posted by Nemesis on:
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http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
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Based on jt51_phasegen.v, from JT51
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*/
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/*
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tab size 4
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*/
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module jt12_pg(
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input clk,
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input clk_en /* synthesis direct_enable */,
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input rst,
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// Channel frequency
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input [10:0] fnum_I,
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input [ 2:0] block_I,
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// Operator multiplying
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input [ 3:0] mul_II,
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// Operator detuning
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input [ 2:0] dt1_I, // same as JT51's DT1
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// phase modulation from LFO
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input [ 6:0] lfo_mod,
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input [ 2:0] pms_I,
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// phase operation
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input pg_rst_II,
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input pg_stop, // not implemented
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output reg [ 4:0] keycode_II,
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output [ 9:0] phase_VIII
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);
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parameter num_ch=6;
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wire [4:0] keycode_I;
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wire signed [5:0] detune_mod_I;
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reg signed [5:0] detune_mod_II;
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wire [16:0] phinc_I;
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reg [16:0] phinc_II;
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wire [19:0] phase_drop, phase_in;
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wire [ 9:0] phase_II;
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always @(posedge clk) if(clk_en) begin
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keycode_II <= keycode_I;
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detune_mod_II <= detune_mod_I;
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phinc_II <= phinc_I;
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end
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jt12_pg_comb u_comb(
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.block ( block_I ),
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.fnum ( fnum_I ),
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// Phase Modulation
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.lfo_mod ( lfo_mod[6:2] ),
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.pms ( pms_I ),
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// Detune
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.detune ( dt1_I ),
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.keycode ( keycode_I ),
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.detune_out ( detune_mod_I ),
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// Phase increment
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.phinc_out ( phinc_I ),
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// Phase add
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.mul ( mul_II ),
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.phase_in ( phase_drop ),
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.pg_rst ( pg_rst_II ),
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.detune_in ( detune_mod_II ),
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.phinc_in ( phinc_II ),
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.phase_out ( phase_in ),
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.phase_op ( phase_II )
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);
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jt12_sh_rst #( .width(20), .stages(4*num_ch) ) u_phsh(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.rst ( rst ),
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.din ( phase_in ),
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.drop ( phase_drop)
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);
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jt12_sh_rst #( .width(10), .stages(6) ) u_pad(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.rst ( rst ),
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.din ( phase_II ),
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.drop ( phase_VIII)
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);
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endmodule
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