mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
51 lines
2.6 KiB
Tcl
51 lines
2.6 KiB
Tcl
# Clock constraints
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create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
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create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
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# Automatically constrain PLL and other generated clocks
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derive_pll_clocks -create_base_clocks
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# Automatically calculate clock uncertainty to jitter and other effects.
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derive_clock_uncertainty
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# Clock groups
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set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
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# SDRAM
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set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -max 6.4 [get_ports SDRAM_DQ[*]]
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set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -min 3.2 [get_ports SDRAM_DQ[*]]
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# SDRAM: max(tCMS, tAS, tDS) = 1.5ns ; max(tCMH, tAH, tDH) = 0.8ns
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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# SDRAM_CLK to internal memory clock
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set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2
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# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 0 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min -5 [get_ports {VGA_*}]
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set_multicycle_path -to [get_ports {VGA_*}] -setup 5
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set_multicycle_path -to [get_ports {VGA_*}] -hold 4
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# Some relaxed constrain for DAC, which is feed by 28 MHz derived clock
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set_multicycle_path -to {dac|*} -setup 3
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set_multicycle_path -to {dac|*} -hold 2
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set_false_path -to [get_ports {AUDIO_L}]
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set_false_path -to [get_ports {AUDIO_R}]
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set_false_path -to [get_ports {LED}]
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set_false_path -from [get_ports {UART_RX}]
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set_multicycle_path -from {tsconf|CPU|*} -setup 2
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set_multicycle_path -from {tsconf|CPU|*} -hold 1
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set_multicycle_path -to {tsconf|CPU|*} -setup 2
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set_multicycle_path -to {tsconf|CPU|*} -hold 1
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set_multicycle_path -to {tsconf|saa1099|*} -setup 2
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set_multicycle_path -to {tsconf|saa1099|*} -hold 1
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set_multicycle_path -to {tsconf|gs_top|gs|CPU|*} -setup 2
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set_multicycle_path -to {tsconf|gs_top|gs|CPU|*} -hold 1
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