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62 lines
1.6 KiB
Verilog
62 lines
1.6 KiB
Verilog
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// This module receives 28 MHz as input clock
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// and makes strobes for all clocked parts
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// clk |—__——__——__——__—| period = 28 duty = 50% phase = 0
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// cnt |< 0>< 1>< 2>< 3>|
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// f0 |————____————____| period = 14 duty = 50% phase = 0
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// f1 |____————____————| period = 14 duty = 50% phase = 180
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// h0 |————————________| period = 7 duty = 50% phase = 0
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// h1 |________————————| period = 7 duty = 50% phase = 180
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// c0 |————____________| period = 7 duty = 25% phase = 0
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// c1 |____————________| period = 7 duty = 25% phase = 90
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// c2 |________————____| period = 7 duty = 25% phase = 180
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// c3 |____________————| period = 7 duty = 25% phase = 270
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`include "tune.v"
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module clock
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(
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input wire clk,
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input wire [1:0] ay_mod,
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output wire f0, f1,
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output wire h0, h1,
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output wire c0, c1, c2, c3,
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output wire ay_clk
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);
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reg [1:0] f = 'b01;
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reg [1:0] h = 'b01;
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reg [3:0] c = 'b0001;
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always @(posedge clk)
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begin
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f <= ~f;
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if (f[1]) h <= ~h;
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c <= {c[2:0], c[3]};
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end
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assign f0 = f[0];
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assign f1 = f[1];
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assign h0 = h[0];
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assign h1 = h[1];
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assign c0 = c[0];
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assign c1 = c[1];
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assign c2 = c[2];
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assign c3 = c[3];
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// AY clock generator
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// ay_mod - clock selection for AY, MHz: 00 - 1.75 / 01 - 1.7733 / 10 - 3.5 / 11 - 3.546
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reg [7:0] skip_cnt = 0;
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reg [3:0] ay_cnt = 0;
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assign ay_clk = ay_mod[1] ? ay_cnt[2] : ay_cnt[3];
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always @(posedge clk)
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begin
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skip_cnt <= skip_cnt[7] ? 8'd73 : skip_cnt - 8'd1;
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ay_cnt <= ay_cnt + (skip_cnt[7] & ay_mod[0] ? 4'd2 : 4'd1);
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end
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endmodule
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