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16 lines
272 B
Verilog
16 lines
272 B
Verilog
`include "tune.v"
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// Reset from MCU must be long enough
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module resetter
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(
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input wire clk,
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input wire rst_in_n, // external asynchronous reset
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output reg rst_out_n // synchronized reset
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);
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always @(posedge clk)
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rst_out_n <= rst_in_n;
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endmodule
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