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34 lines
941 B
Verilog
34 lines
941 B
Verilog
// This module receives 28 MHz as input clock
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// and strobes strobes for all clocked parts
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// clk|-__--__--__--__-| period = 28 duty = 50% phase = 0
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// cnt|< 0>< 1>< 2>< 3>|
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// f0 |----____----____| period = 14 duty = 50% phase = 0
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// f1 |____----____----| period = 14 duty = 50% phase = 180
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// h0 |--------________| period = 7 duty = 50% phase = 0
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// h1 |________--------| period = 7 duty = 50% phase = 180
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// c0 |----____________| period = 7 duty = 25% phase = 0
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// c1 |____----________| period = 7 duty = 25% phase = 90
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// c2 |________----____| period = 7 duty = 25% phase = 180
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// c3 |____________----| period = 7 duty = 25% phase = 270
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module clock
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(
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input wire clk,
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output reg f0, f1,
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output reg h0, h1,
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output reg c0, c1, c2, c3
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);
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reg [1:0] cnt;
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always @(posedge clk) begin
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cnt <= cnt + 2'b1;
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{f1, f0} <= 2'b1 << cnt[0];
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{h1, h0} <= 2'b1 << cnt[1];
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{c3, c2, c1, c0} <= 4'b1 << cnt;
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end
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endmodule
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