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https://github.com/UzixLS/TSConf_MiST.git
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141 lines
3.5 KiB
Verilog
141 lines
3.5 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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YM3438_APL.pdf
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Timer A = 144*(1024-NA)/Phi M
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Timer B = 2304*(256-NB)/Phi M
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*/
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module jt12_timers(
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input clk,
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input rst,
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input clk_en /* synthesis direct_enable */,
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input zero,
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input [9:0] value_A,
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input [7:0] value_B,
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input load_A,
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input load_B,
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input clr_flag_A,
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input clr_flag_B,
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input enable_irq_A,
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input enable_irq_B,
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output flag_A,
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output flag_B,
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output overflow_A,
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output irq_n
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);
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parameter num_ch = 6;
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assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
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/*
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reg zero2;
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always @(posedge clk, posedge rst) begin
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if( rst )
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zero2 <= 0;
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else if(clk_en) begin
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if( zero ) zero2 <= ~zero;
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end
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end
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wire zero = num_ch == 6 ? zero : (zero2&zero);
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*/
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jt12_timer #(.CW(10)) timer_A(
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.clk ( clk ),
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.rst ( rst ),
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.cen ( clk_en ),
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.zero ( zero ),
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.start_value( value_A ),
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.load ( load_A ),
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.clr_flag ( clr_flag_A ),
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.flag ( flag_A ),
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.overflow ( overflow_A )
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);
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jt12_timer #(.CW(8),.FREE_EN(1)) timer_B(
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.clk ( clk ),
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.rst ( rst ),
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.cen ( clk_en ),
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.zero ( zero ),
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.start_value( value_B ),
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.load ( load_B ),
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.clr_flag ( clr_flag_B ),
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.flag ( flag_B ),
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.overflow ( )
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);
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endmodule
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module jt12_timer #(parameter
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CW = 8, // counter bit width. This is the counter that can be loaded
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FW = 4, // number of bits for the free-running counter
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FREE_EN = 0 // enables a 4-bit free enable count
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) (
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input rst,
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input clk,
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input cen,
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input zero,
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input [CW-1:0] start_value,
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input load,
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input clr_flag,
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output reg flag,
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output reg overflow
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);
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/* verilator lint_off WIDTH */
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reg load_l;
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reg [CW-1:0] cnt, next;
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reg [FW-1:0] free_cnt, free_next;
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reg free_ov;
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always@(posedge clk, posedge rst)
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if( rst )
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flag <= 1'b0;
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else /*if(cen)*/ begin
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if( clr_flag )
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flag <= 1'b0;
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else if( cen && zero && load && overflow ) flag<=1'b1;
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end
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always @(*) begin
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{free_ov, free_next} = { 1'b0, free_cnt} + 1'b1;
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{overflow, next } = { 1'b0, cnt } + (FREE_EN ? free_ov : 1'b1);
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end
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always @(posedge clk) begin
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load_l <= load;
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if( !load_l && load ) begin
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cnt <= start_value;
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end else if( cen && zero && load )
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cnt <= overflow ? start_value : next;
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end
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// Free running counter
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always @(posedge clk) begin
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if( rst ) begin
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free_cnt <= 0;
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end else if( cen && zero ) begin
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free_cnt <= free_next;
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end
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end
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/* verilator lint_on WIDTH */
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endmodule
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