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45 lines
1.3 KiB
VHDL
45 lines
1.3 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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package jt12 is
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component jt12
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port
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(
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rst : in std_logic;
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clk : in std_logic; -- CPU clock
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cen : in std_logic := '1'; -- optional clock enable, if not needed leave as '1'
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din : in std_logic_vector(7 downto 0);
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addr : in std_logic_vector(1 downto 0);
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cs_n : in std_logic;
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wr_n : in std_logic;
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dout : out std_logic_vector(7 downto 0);
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irq_n : out std_logic;
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en_hifi_pcm: in std_logic; -- set high to use interpolation on PCM samples
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-- combined output
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snd_right : out std_logic_vector(15 downto 0); -- signed
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snd_left : out std_logic_vector(15 downto 0); -- signed
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snd_sample : out std_logic
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);
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end component;
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component jt12_genmix
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port
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(
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rst : in std_logic;
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clk : in std_logic; -- expects 54 MHz clock
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fm_left : in std_logic_vector(15 downto 0); -- FM at 55kHz
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fm_right: in std_logic_vector(15 downto 0); -- FM at 55kHz
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psg_snd : in std_logic_vector(10 downto 0); -- PSG at 220kHz
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fm_en : in std_logic;
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psg_en : in std_logic;
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-- Mixed sound at 54 MHz
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snd_left : out std_logic_vector(15 downto 0);
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snd_right : out std_logic_vector(15 downto 0)
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);
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end component;
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end;
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