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https://github.com/UzixLS/TSConf_MiST.git
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153 lines
5.0 KiB
VHDL
153 lines
5.0 KiB
VHDL
--------------------------------------------------------------------------------
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-- ****
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-- T80(c) core. Attempt to finish all undocumented features and provide
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-- accurate timings.
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-- Version 350.
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-- Copyright (c) 2018 Sorgelig
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-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
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-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
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-- correct implementation is still unclear.
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--
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-- ****
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-- T80(b) core. In an effort to merge and maintain bug fixes ....
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--
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--
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-- Ver 300 started tidyup
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-- MikeJ March 2005
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-- Latest version from www.fpgaarcade.com (original www.opencores.org)
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--
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-- ****
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--
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-- T80 Registers, technology independent
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--
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-- Version : 0244
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t51/
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--
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-- Limitations :
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--
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-- File history :
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--
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-- 0242 : Initial release
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--
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-- 0244 : Changed to single register file
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity T80_Reg is
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port(
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Clk : in std_logic;
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CEN : in std_logic;
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WEH : in std_logic;
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WEL : in std_logic;
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AddrA : in std_logic_vector(2 downto 0);
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AddrB : in std_logic_vector(2 downto 0);
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AddrC : in std_logic_vector(2 downto 0);
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DIH : in std_logic_vector(7 downto 0);
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DIL : in std_logic_vector(7 downto 0);
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DOAH : out std_logic_vector(7 downto 0);
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DOAL : out std_logic_vector(7 downto 0);
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DOBH : out std_logic_vector(7 downto 0);
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DOBL : out std_logic_vector(7 downto 0);
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DOCH : out std_logic_vector(7 downto 0);
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DOCL : out std_logic_vector(7 downto 0);
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DOR : out std_logic_vector(127 downto 0);
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DIRSet : in std_logic;
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DIR : in std_logic_vector(127 downto 0)
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);
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end T80_Reg;
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architecture rtl of T80_Reg is
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type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
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signal RegsH : Register_Image(0 to 7);
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signal RegsL : Register_Image(0 to 7);
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begin
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process (Clk)
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begin
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if rising_edge(Clk) then
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if DIRSet = '1' then
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RegsL(0) <= DIR( 7 downto 0);
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RegsH(0) <= DIR( 15 downto 8);
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RegsL(1) <= DIR( 23 downto 16);
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RegsH(1) <= DIR( 31 downto 24);
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RegsL(2) <= DIR( 39 downto 32);
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RegsH(2) <= DIR( 47 downto 40);
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RegsL(3) <= DIR( 55 downto 48);
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RegsH(3) <= DIR( 63 downto 56);
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RegsL(4) <= DIR( 71 downto 64);
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RegsH(4) <= DIR( 79 downto 72);
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RegsL(5) <= DIR( 87 downto 80);
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RegsH(5) <= DIR( 95 downto 88);
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RegsL(6) <= DIR(103 downto 96);
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RegsH(6) <= DIR(111 downto 104);
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RegsL(7) <= DIR(119 downto 112);
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RegsH(7) <= DIR(127 downto 120);
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elsif CEN = '1' then
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if WEH = '1' then
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RegsH(to_integer(unsigned(AddrA))) <= DIH;
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end if;
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if WEL = '1' then
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RegsL(to_integer(unsigned(AddrA))) <= DIL;
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end if;
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end if;
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end if;
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end process;
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DOAH <= RegsH(to_integer(unsigned(AddrA)));
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DOAL <= RegsL(to_integer(unsigned(AddrA)));
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DOBH <= RegsH(to_integer(unsigned(AddrB)));
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DOBL <= RegsL(to_integer(unsigned(AddrB)));
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DOCH <= RegsH(to_integer(unsigned(AddrC)));
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DOCL <= RegsL(to_integer(unsigned(AddrC)));
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DOR <= RegsH(7) & RegsL(7) & RegsH(6) & RegsL(6) & RegsH(5) & RegsL(5) & RegsH(4) & RegsL(4) & RegsH(3) & RegsL(3) & RegsH(2) & RegsL(2) & RegsH(1) & RegsL(1) & RegsH(0) & RegsL(0);
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end;
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