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114 lines
2.6 KiB
Verilog
114 lines
2.6 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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YM3438_APL.pdf
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Timer A = 144*(1024-NA)/Phi M
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Timer B = 2304*(256-NB)/Phi M
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*/
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`timescale 1ns / 1ps
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module jt12_timers(
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input clk,
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input rst,
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input clk_en, // clock enable
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input [9:0] value_A,
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input [7:0] value_B,
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input load_A,
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input load_B,
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input clr_flag_A,
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input clr_flag_B,
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input enable_irq_A,
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input enable_irq_B,
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output flag_A,
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output flag_B,
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output overflow_A,
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output irq_n
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);
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assign irq_n = ~( (flag_A&enable_irq_A) | (flag_B&enable_irq_B) );
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jt12_timer #(.mult_width(5), .mult_max(24), .counter_width(10))
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timer_A(
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.clk ( clk ),
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.rst ( rst ),
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.clk_en ( clk_en ),
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.start_value( value_A ),
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.load ( load_A ),
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.clr_flag ( clr_flag_A),
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.flag ( flag_A ),
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.overflow ( overflow_A)
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);
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jt12_timer #(.mult_width(9), .mult_max(384), .counter_width(8))
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timer_B(
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.clk ( clk ),
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.rst ( rst ),
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.clk_en ( clk_en ),
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.start_value( value_B ),
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.load ( load_B ),
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.clr_flag ( clr_flag_B),
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.flag ( flag_B ),
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.overflow ( )
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);
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endmodule
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module jt12_timer #(parameter counter_width = 10, mult_width=5, mult_max=4 )
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(
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input clk,
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input rst,
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(* direct_enable *) input clk_en,
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input [counter_width-1:0] start_value,
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input load,
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input clr_flag,
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output reg flag,
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output reg overflow
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);
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reg [ mult_width-1:0] mult;
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reg [counter_width-1:0] cnt;
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always@(posedge clk)
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if( clr_flag || rst)
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flag <= 1'b0;
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else if(overflow) flag<=1'b1;
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reg [mult_width+counter_width-1:0] next, init;
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always @(*) begin
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if( mult<mult_max ) begin
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// mult not meant to overflow in this line
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{overflow, next } = { {1'b0, cnt}, mult+1'b1 } ;
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end else begin
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{overflow, next } = { {1'b0, cnt}+1'b1, {mult_width{1'b0}} };
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end
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init = { start_value, {mult_width{1'b0}} };
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end
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always @(posedge clk)
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if( ~load || rst) begin
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mult <= { (mult_width){1'b0} };
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cnt <= start_value;
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end
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else if( clk_en )
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{ cnt, mult } <= overflow ? init : next;
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endmodule
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