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109 lines
2.7 KiB
Verilog
109 lines
2.7 KiB
Verilog
module jt12_pcm(
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input rst,
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input clk,
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(* direct_enable *) input clk_en,
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input zero,
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input signed [8:0] pcm,
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input pcm_wr,
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output reg signed [8:0] pcm_resampled
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);
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// reg [2:0] ratesel;
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// reg [3:0] cnt8;
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// reg wrcnt, wrclr;
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reg last_zero;
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wire zero_edge = !last_zero && zero;
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/*
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always @(posedge clk)
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if(rst) begin
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cnt8 <= 4'd0;
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wrclr <= 1'd0;
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ratesel <= 3'd1;
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wrcnt <= 1'b0;
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end else if(clk_en) begin
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if( pcm_wr ) begin
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if( wrcnt ) begin
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// case( cnt8[3:2] )
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// 2'd3: ratesel <= 3'b111; // x8
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// 2'd2: ratesel <= 3'b011; // x4
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// 2'd1: ratesel <= 3'b001; // x2
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// 2'd0: ratesel <= 3'b000; // x1
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// endcase
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cnt8 <= 4'd0;
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wrcnt <= 1'b0;
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end
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else wrcnt <= 1'b1;
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end else
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if( cnt8!=4'hf && zero ) cnt8 <= cnt8 + 4'd1;
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end
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*/
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// up-rate PCM samples
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reg rate1, rate2; //, rate4, rate8;
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reg cen1, cen2; //, cen4, cen8;
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always @(posedge clk)
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if(rst)
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rate2 <= 1'b0;
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else begin
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last_zero <= zero;
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rate1 <= zero_edge;
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if(zero_edge) begin
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rate2 <= ~rate2;
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// if(rate2) begin
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// rate4 <= ~rate4;
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// if(rate4) rate8<=~rate8;
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// end
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end
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end
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always @(negedge clk) begin
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cen1 <= rate1;
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cen2 <= rate1 && rate2;
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// cen4 <= rate1 && rate2 && rate4;
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// cen8 <= rate1 && rate2 && rate4 && rate8;
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end
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wire signed [8:0] pcm3; //,pcm2, pcm1;
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//always @(posedge clk) if( clk_en )
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// pcm_resampled <= ratesel[0] ? pcm3 : pcm;
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always @(*)
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pcm_resampled = pcm3;
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// rate x2
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//wire signed [8:0] pcm_in2 = ratesel[1] ? pcm2 : pcm;
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jt12_interpol #(.calcw(10),.inw(9),.rate(2),.m(1),.n(2))
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u_uprate_3(
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.clk ( clk ),
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.rst ( rst ),
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.cen_in ( cen2 ),
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.cen_out( cen1 ),
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// .snd_in ( pcm_in2 ),
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.snd_in ( pcm ),
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.snd_out( pcm3 )
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);
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/*
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// rate x2
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wire signed [8:0] pcm_in1 = ratesel[2] ? pcm1 : pcm;
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jt12_interpol #(.calcw(10),.inw(9),.rate(2),.m(1),.n(2))
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u_uprate_2(
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.clk ( clk ),
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.rst ( rst ),
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.cen_in ( cen4 ),
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.cen_out( cen2 ),
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.snd_in ( pcm_in1 ),
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.snd_out( pcm2 )
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);
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// rate x2
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jt12_interpol #(.calcw(10),.inw(9),.rate(2),.m(1),.n(2))
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u_uprate_1(
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.clk ( clk ),
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.rst ( rst ),
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.cen_in ( cen8 ),
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.cen_out( cen4 ),
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.snd_in ( pcm ),
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.snd_out( pcm1 )
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);
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*/
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endmodule // jt12_pcm
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