mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-19 15:21:47 +03:00
506 lines
13 KiB
Verilog
506 lines
13 KiB
Verilog
`timescale 1ns / 1ps
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/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-1-2017
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*/
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module jt12_op(
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input rst,
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input clk,
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input clk_en,
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input [9:0] pg_phase_VIII,
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input [9:0] eg_atten_IX, // output from envelope generator
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input [2:0] fb_II, // voice feedback
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input xuse_prevprev1,
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input xuse_prev2,
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input xuse_internal,
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input yuse_prev1,
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input yuse_prev2,
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input yuse_internal,
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input test_214,
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input s1_enters,
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input s2_enters,
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input s3_enters,
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input s4_enters,
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input zero,
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output signed [ 8:0] op_result,
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output signed [13:0] full_result
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);
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/* enters exits
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S1 S2
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S3 S4
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S2 S1
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S4 S3
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*/
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reg [13:0] op_result_internal, op_XII;
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reg [11:0] atten_internal_IX;
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assign op_result = op_result_internal[13:5];
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assign full_result = op_result_internal;
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parameter num_ch = 6;
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reg signbit_IX, signbit_X, signbit_XI;
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reg [11:0] totalatten_X;
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wire [13:0] prev1, prevprev1, prev2;
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reg [13:0] prev1_din, prevprev1_din, prev2_din;
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always @(*)
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if( num_ch==3 ) begin
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prev1_din = s1_enters ? op_result_internal : prev1;
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prevprev1_din = s3_enters ? op_result_internal : prevprev1;
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prev2_din = s2_enters ? op_result_internal : prev2;
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end else begin // 6 channels
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prev1_din = s2_enters ? op_result_internal : prev1;
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prevprev1_din = s2_enters ? prev1 : prevprev1;
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prev2_din = s1_enters ? op_result_internal : prev2;
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end
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jt12_sh #( .width(14), .stages(num_ch)) prev1_buffer(
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// .rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.din ( prev1_din ),
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.drop ( prev1 )
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);
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jt12_sh #( .width(14), .stages(num_ch)) prevprev1_buffer(
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// .rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.din ( prevprev1_din ),
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.drop ( prevprev1 )
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);
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jt12_sh #( .width(14), .stages(num_ch)) prev2_buffer(
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// .rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.din ( prev2_din ),
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.drop ( prev2 )
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);
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reg [10:0] subtresult;
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reg [12:0] shifter, shifter_2, shifter_3;
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// REGISTER/CYCLE 1
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// Creation of phase modulation (FM) feedback signal, before shifting
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reg [13:0] x, y;
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reg [14:0] xs, ys, pm_preshift_II;
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reg s1_II;
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always @(*) begin
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casez( {xuse_prevprev1, xuse_prev2, xuse_internal })
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3'b1??: x = prevprev1;
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3'b01?: x = prev2;
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3'b001: x = op_result_internal;
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default: x = 14'd0;
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endcase
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casez( {yuse_prev1, yuse_prev2, yuse_internal })
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3'b1??: y = prev1;
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3'b01?: y = prev2;
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3'b001: y = op_result_internal;
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default: y = 14'd0;
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endcase
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xs = { x[13], x }; // sign-extend
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ys = { y[13], y }; // sign-extend
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end
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always @(posedge clk) if( clk_en ) begin
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pm_preshift_II <= xs + ys; // carry is discarded
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s1_II <= s1_enters;
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end
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/* REGISTER/CYCLE 2-7 (also YM2612 extra cycles 1-6)
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Shifting of FM feedback signal, adding phase from PG to FM phase
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In YM2203, phasemod_II is not registered at all, it is latched on the first edge
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in add_pg_phase and the second edge is the output of add_pg_phase. In the YM2612, there
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are 6 cycles worth of registers between the generated (non-registered) phasemod_II signal
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and the input to add_pg_phase. */
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reg [9:0] phasemod_II;
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wire [9:0] phasemod_VIII;
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always @(*) begin
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// Shift FM feedback signal
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if (!s1_II ) // Not S1
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phasemod_II = pm_preshift_II[10:1]; // Bit 0 of pm_preshift_II is never used
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else // S1
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case( fb_II )
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3'd0: phasemod_II = 10'd0;
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3'd1: phasemod_II = { {4{pm_preshift_II[14]}}, pm_preshift_II[14:9] };
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3'd2: phasemod_II = { {3{pm_preshift_II[14]}}, pm_preshift_II[14:8] };
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3'd3: phasemod_II = { {2{pm_preshift_II[14]}}, pm_preshift_II[14:7] };
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3'd4: phasemod_II = { pm_preshift_II[14], pm_preshift_II[14:6] };
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3'd5: phasemod_II = pm_preshift_II[14:5];
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3'd6: phasemod_II = pm_preshift_II[13:4];
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3'd7: phasemod_II = pm_preshift_II[12:3];
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endcase
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end
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// REGISTER/CYCLE 2-7
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//generate
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// if( num_ch==6 )
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jt12_sh #( .width(10), .stages(6)) phasemod_sh(
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.clk ( clk ),
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.clk_en ( clk_en),
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.din ( phasemod_II ),
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.drop ( phasemod_VIII )
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);
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// else begin
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// assign phasemod_VIII = phasemod_II;
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// end
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// endgenerate
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// REGISTER/CYCLE 8
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reg [ 9:0] phase;
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// Sets the maximum number of fanouts for a register or combinational
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// cell. The Quartus II software will replicate the cell and split
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// the fanouts among the duplicates until the fanout of each cell
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// is below the maximum.
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reg [ 7:0] aux_VIII;
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always @(*) begin
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phase = phasemod_VIII + pg_phase_VIII;
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aux_VIII= phase[7:0] ^ {8{~phase[8]}};
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end
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always @(posedge clk) if( clk_en ) begin
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signbit_IX <= phase[9];
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end
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wire [11:0] logsin_IX;
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jt12_logsin u_logsin (
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.clk ( clk ),
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.clk_en ( clk_en ),
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.addr ( aux_VIII[7:0] ),
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.logsin ( logsin_IX )
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);
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// REGISTER/CYCLE 9
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// Sine table
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// Main sine table body
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always @(*) begin
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subtresult = eg_atten_IX + logsin_IX[11:2];
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atten_internal_IX = { subtresult[9:0], logsin_IX[1:0] } | {12{subtresult[10]}};
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end
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wire [9:0] mantissa_X;
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reg [9:0] mantissa_XI;
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reg [3:0] exponent_X, exponent_XI;
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jt12_exprom u_exprom(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.addr ( atten_internal_IX[7:0] ),
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.exp ( mantissa_X )
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);
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always @(posedge clk) if( clk_en ) begin
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exponent_X <= atten_internal_IX[11:8];
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signbit_X <= signbit_IX;
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end
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always @(posedge clk) if( clk_en ) begin
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mantissa_XI <= mantissa_X;
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exponent_XI <= exponent_X;
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signbit_XI <= signbit_X;
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end
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// REGISTER/CYCLE 11
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// Introduce test bit as MSB, 2's complement & Carry-out discarded
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always @(*) begin
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// Floating-point to integer, and incorporating sign bit
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// Two-stage shifting of mantissa_XI by exponent_XI
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shifter = { 3'b001, mantissa_XI };
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case( ~exponent_XI[1:0] )
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2'b00: shifter_2 = { 1'b0, shifter[12:1] }; // LSB discarded
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2'b01: shifter_2 = shifter;
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2'b10: shifter_2 = { shifter[11:0], 1'b0 };
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2'b11: shifter_2 = { shifter[10:0], 2'b0 };
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endcase
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case( ~exponent_XI[3:2] )
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2'b00: shifter_3 = {12'b0, shifter_2[12] };
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2'b01: shifter_3 = { 8'b0, shifter_2[12:8] };
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2'b10: shifter_3 = { 4'b0, shifter_2[12:4] };
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2'b11: shifter_3 = shifter_2;
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endcase
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end
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always @(posedge clk) if( clk_en ) begin
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// REGISTER CYCLE 11
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op_XII <= ({ test_214, shifter_3 } ^ {14{signbit_XI}}) + {13'd0,signbit_XI};
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// REGISTER CYCLE 12
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// Extra register, take output after here
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op_result_internal <= op_XII;
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end
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`ifdef SIMULATION
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/* verilator lint_off PINMISSING */
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reg [4:0] sep24_cnt;
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wire signed [13:0] op_ch0s1, op_ch1s1, op_ch2s1, op_ch3s1,
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op_ch4s1, op_ch5s1, op_ch0s2, op_ch1s2,
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op_ch2s2, op_ch3s2, op_ch4s2, op_ch5s2,
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op_ch0s3, op_ch1s3, op_ch2s3, op_ch3s3,
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op_ch4s3, op_ch5s3, op_ch0s4, op_ch1s4,
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op_ch2s4, op_ch3s4, op_ch4s4, op_ch5s4;
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always @(posedge clk ) if( clk_en ) begin
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sep24_cnt <= !zero ? sep24_cnt+1'b1 : 5'd0;
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end
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sep24 #( .width(14), .pos0(13)) opsep
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(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.mixed ( op_result_internal ),
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.mask ( 24'd0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (op_ch0s1),
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.ch1s1 (op_ch1s1),
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.ch2s1 (op_ch2s1),
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.ch3s1 (op_ch3s1),
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.ch4s1 (op_ch4s1),
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.ch5s1 (op_ch5s1),
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.ch0s2 (op_ch0s2),
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.ch1s2 (op_ch1s2),
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.ch2s2 (op_ch2s2),
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.ch3s2 (op_ch3s2),
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.ch4s2 (op_ch4s2),
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.ch5s2 (op_ch5s2),
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.ch0s3 (op_ch0s3),
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.ch1s3 (op_ch1s3),
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.ch2s3 (op_ch2s3),
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.ch3s3 (op_ch3s3),
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.ch4s3 (op_ch4s3),
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.ch5s3 (op_ch5s3),
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.ch0s4 (op_ch0s4),
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.ch1s4 (op_ch1s4),
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.ch2s4 (op_ch2s4),
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.ch3s4 (op_ch3s4),
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.ch4s4 (op_ch4s4),
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.ch5s4 (op_ch5s4)
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);
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wire signed [8:0] acc_ch0s1, acc_ch1s1, acc_ch2s1, acc_ch3s1,
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acc_ch4s1, acc_ch5s1, acc_ch0s2, acc_ch1s2,
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acc_ch2s2, acc_ch3s2, acc_ch4s2, acc_ch5s2,
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acc_ch0s3, acc_ch1s3, acc_ch2s3, acc_ch3s3,
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acc_ch4s3, acc_ch5s3, acc_ch0s4, acc_ch1s4,
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acc_ch2s4, acc_ch3s4, acc_ch4s4, acc_ch5s4;
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sep24 #( .width(9), .pos0(13)) accsep
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(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.mixed ( op_result_internal[13:5] ),
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.mask ( 24'd0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (acc_ch0s1),
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.ch1s1 (acc_ch1s1),
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.ch2s1 (acc_ch2s1),
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.ch3s1 (acc_ch3s1),
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.ch4s1 (acc_ch4s1),
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.ch5s1 (acc_ch5s1),
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.ch0s2 (acc_ch0s2),
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.ch1s2 (acc_ch1s2),
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.ch2s2 (acc_ch2s2),
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.ch3s2 (acc_ch3s2),
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.ch4s2 (acc_ch4s2),
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.ch5s2 (acc_ch5s2),
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.ch0s3 (acc_ch0s3),
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.ch1s3 (acc_ch1s3),
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.ch2s3 (acc_ch2s3),
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.ch3s3 (acc_ch3s3),
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.ch4s3 (acc_ch4s3),
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.ch5s3 (acc_ch5s3),
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.ch0s4 (acc_ch0s4),
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.ch1s4 (acc_ch1s4),
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.ch2s4 (acc_ch2s4),
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.ch3s4 (acc_ch3s4),
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.ch4s4 (acc_ch4s4),
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.ch5s4 (acc_ch5s4)
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);
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wire signed [9:0] pm_ch0s1, pm_ch1s1, pm_ch2s1, pm_ch3s1,
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pm_ch4s1, pm_ch5s1, pm_ch0s2, pm_ch1s2,
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pm_ch2s2, pm_ch3s2, pm_ch4s2, pm_ch5s2,
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pm_ch0s3, pm_ch1s3, pm_ch2s3, pm_ch3s3,
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pm_ch4s3, pm_ch5s3, pm_ch0s4, pm_ch1s4,
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pm_ch2s4, pm_ch3s4, pm_ch4s4, pm_ch5s4;
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sep24 #( .width(10), .pos0( 18 ) ) pmsep
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(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.mixed ( phasemod_VIII ),
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.mask ( 24'd0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (pm_ch0s1),
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.ch1s1 (pm_ch1s1),
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.ch2s1 (pm_ch2s1),
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.ch3s1 (pm_ch3s1),
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.ch4s1 (pm_ch4s1),
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.ch5s1 (pm_ch5s1),
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.ch0s2 (pm_ch0s2),
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.ch1s2 (pm_ch1s2),
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.ch2s2 (pm_ch2s2),
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.ch3s2 (pm_ch3s2),
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.ch4s2 (pm_ch4s2),
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.ch5s2 (pm_ch5s2),
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.ch0s3 (pm_ch0s3),
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.ch1s3 (pm_ch1s3),
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.ch2s3 (pm_ch2s3),
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.ch3s3 (pm_ch3s3),
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.ch4s3 (pm_ch4s3),
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.ch5s3 (pm_ch5s3),
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.ch0s4 (pm_ch0s4),
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.ch1s4 (pm_ch1s4),
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.ch2s4 (pm_ch2s4),
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.ch3s4 (pm_ch3s4),
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.ch4s4 (pm_ch4s4),
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.ch5s4 (pm_ch5s4)
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);
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wire [9:0] phase_ch0s1, phase_ch1s1, phase_ch2s1, phase_ch3s1,
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phase_ch4s1, phase_ch5s1, phase_ch0s2, phase_ch1s2,
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phase_ch2s2, phase_ch3s2, phase_ch4s2, phase_ch5s2,
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phase_ch0s3, phase_ch1s3, phase_ch2s3, phase_ch3s3,
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phase_ch4s3, phase_ch5s3, phase_ch0s4, phase_ch1s4,
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phase_ch2s4, phase_ch3s4, phase_ch4s4, phase_ch5s4;
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sep24 #( .width(10), .pos0( 18 ) ) phsep
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(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.mixed ( phase ),
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.mask ( 24'd0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (phase_ch0s1),
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.ch1s1 (phase_ch1s1),
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.ch2s1 (phase_ch2s1),
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.ch3s1 (phase_ch3s1),
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.ch4s1 (phase_ch4s1),
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.ch5s1 (phase_ch5s1),
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.ch0s2 (phase_ch0s2),
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.ch1s2 (phase_ch1s2),
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.ch2s2 (phase_ch2s2),
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.ch3s2 (phase_ch3s2),
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.ch4s2 (phase_ch4s2),
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.ch5s2 (phase_ch5s2),
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.ch0s3 (phase_ch0s3),
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.ch1s3 (phase_ch1s3),
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.ch2s3 (phase_ch2s3),
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.ch3s3 (phase_ch3s3),
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.ch4s3 (phase_ch4s3),
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.ch5s3 (phase_ch5s3),
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.ch0s4 (phase_ch0s4),
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.ch1s4 (phase_ch1s4),
|
|
.ch2s4 (phase_ch2s4),
|
|
.ch3s4 (phase_ch3s4),
|
|
.ch4s4 (phase_ch4s4),
|
|
.ch5s4 (phase_ch5s4)
|
|
);
|
|
|
|
wire [9:0] eg_ch0s1, eg_ch1s1, eg_ch2s1, eg_ch3s1, eg_ch4s1, eg_ch5s1,
|
|
eg_ch0s2, eg_ch1s2, eg_ch2s2, eg_ch3s2, eg_ch4s2, eg_ch5s2,
|
|
eg_ch0s3, eg_ch1s3, eg_ch2s3, eg_ch3s3, eg_ch4s3, eg_ch5s3,
|
|
eg_ch0s4, eg_ch1s4, eg_ch2s4, eg_ch3s4, eg_ch4s4, eg_ch5s4;
|
|
|
|
|
|
sep24 #( .width(10), .pos0(17) ) egsep
|
|
(
|
|
.clk ( clk ),
|
|
.clk_en ( clk_en ),
|
|
.mixed ( eg_atten_IX ),
|
|
.mask ( 24'd0 ),
|
|
.cnt ( sep24_cnt ),
|
|
|
|
.ch0s1 (eg_ch0s1),
|
|
.ch1s1 (eg_ch1s1),
|
|
.ch2s1 (eg_ch2s1),
|
|
.ch3s1 (eg_ch3s1),
|
|
.ch4s1 (eg_ch4s1),
|
|
.ch5s1 (eg_ch5s1),
|
|
|
|
.ch0s2 (eg_ch0s2),
|
|
.ch1s2 (eg_ch1s2),
|
|
.ch2s2 (eg_ch2s2),
|
|
.ch3s2 (eg_ch3s2),
|
|
.ch4s2 (eg_ch4s2),
|
|
.ch5s2 (eg_ch5s2),
|
|
|
|
.ch0s3 (eg_ch0s3),
|
|
.ch1s3 (eg_ch1s3),
|
|
.ch2s3 (eg_ch2s3),
|
|
.ch3s3 (eg_ch3s3),
|
|
.ch4s3 (eg_ch4s3),
|
|
.ch5s3 (eg_ch5s3),
|
|
|
|
.ch0s4 (eg_ch0s4),
|
|
.ch1s4 (eg_ch1s4),
|
|
.ch2s4 (eg_ch2s4),
|
|
.ch3s4 (eg_ch3s4),
|
|
.ch4s4 (eg_ch4s4),
|
|
.ch5s4 (eg_ch5s4)
|
|
);
|
|
/* verilator lint_on PINMISSING */
|
|
`endif
|
|
|
|
|
|
endmodule
|