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122 lines
2.9 KiB
Verilog
122 lines
2.9 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 29-10-2018
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*/
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module jt12_eg_ctrl(
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input keyon_now,
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input keyoff_now,
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input [2:0] state_in,
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input [9:0] eg,
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// envelope configuration
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input [4:0] arate, // attack rate
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input [4:0] rate1, // decay rate
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input [4:0] rate2, // sustain rate
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input [3:0] rrate,
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input [3:0] sl, // sustain level
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// SSG operation
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input ssg_en,
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input [2:0] ssg_eg,
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// SSG output inversion
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input ssg_inv_in,
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output reg ssg_inv_out,
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output reg [4:0] base_rate,
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output reg [2:0] state_next,
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output reg pg_rst
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);
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localparam ATTACK = 3'b001,
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DECAY = 3'b010,
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HOLD = 3'b100,
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RELEASE= 3'b000; // default state is release
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// wire is_decaying = state_in[1] | state_in[2];
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reg [4:0] sustain;
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always @(*)
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if( sl == 4'd15 )
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sustain = 5'h1f; // 93dB
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else
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sustain = {1'b0, sl};
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wire ssg_en_out;
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reg ssg_en_in, ssg_pg_rst;
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// aliases
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wire ssg_att = ssg_eg[2];
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wire ssg_alt = ssg_eg[1];
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wire ssg_hold = ssg_eg[0] & ssg_en;
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reg ssg_over;
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always @(*) begin
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ssg_over = ssg_en && eg[9]; // eg >=10'h200
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ssg_pg_rst = ssg_over && !( ssg_alt || ssg_hold );
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pg_rst = keyon_now | ssg_pg_rst;
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end
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always @(*)
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casez ( { keyoff_now, keyon_now, state_in} )
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5'b01_???: begin // key on
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base_rate = arate;
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state_next = ATTACK;
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ssg_inv_out = ssg_att & ssg_en;
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end
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{2'b00, ATTACK}:
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if( eg==10'd0 ) begin
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base_rate = rate1;
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state_next = DECAY;
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ssg_inv_out = ssg_inv_in;
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end
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else begin
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base_rate = arate;
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state_next = ATTACK;
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ssg_inv_out = ssg_inv_in;
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end
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{2'b00, DECAY}: begin
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if( ssg_over ) begin
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base_rate = ssg_hold ? 5'd0 : arate;
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state_next = ssg_hold ? HOLD : ATTACK;
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ssg_inv_out = ssg_en & (ssg_alt ^ ssg_inv_in);
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end
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else begin
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base_rate = eg[9:5] >= sustain ? rate2 : rate1;
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state_next = DECAY;
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ssg_inv_out = ssg_inv_in;
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end
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end
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{2'b00, HOLD}: begin
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base_rate = 5'd0;
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state_next = HOLD;
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ssg_inv_out = ssg_inv_in;
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end
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default: begin // RELEASE, note that keyoff_now==1 will enter this state too
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base_rate = { rrate, 1'b1 };
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state_next = RELEASE; // release
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ssg_inv_out = 1'b0; // this can produce a glitch in the output
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// But to release from SSG cannot be done nicely while
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// inverting the ouput
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end
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endcase
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endmodule // jt12_eg_ctrl
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