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https://github.com/UzixLS/TSConf_MiST.git
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73 lines
2.4 KiB
Verilog
73 lines
2.4 KiB
Verilog
/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-12-2018
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*/
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// Wrapper to output only combined channels. Defaults to YM2203 mode.
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module jt03(
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input rst, // rst should be at least 6 clk&cen cycles long
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input clk, // CPU clock
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input cen, // optional clock enable, it not needed leave as 1'b1
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input [7:0] din,
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input addr,
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input cs_n,
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input wr_n,
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output [7:0] dout,
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output irq_n,
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// Separated output
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output [ 7:0] psg_A,
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output [ 7:0] psg_B,
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output [ 7:0] psg_C,
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output signed [15:0] fm_snd,
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// combined output
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output [ 9:0] psg_snd,
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output signed [15:0] snd,
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output snd_sample
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);
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jt12_top #(.use_lfo(0),.use_ssg(1), .num_ch(3), .use_pcm(0), .use_lr(0))
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u_jt12(
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.rst ( rst ), // rst should be at least 6 clk&cen cycles long
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.clk ( clk ), // CPU clock
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.cen ( cen ), // optional clock enable, it not needed leave as 1'b1
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.din ( din ),
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.addr ( {1'b0, addr} ),
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.cs_n ( cs_n ),
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.wr_n ( wr_n ),
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.dout ( dout ),
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.irq_n ( irq_n ),
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// Separated output
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.psg_A ( psg_A ),
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.psg_B ( psg_B ),
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.psg_C ( psg_C ),
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.psg_snd ( psg_snd ),
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.fm_snd_left ( fm_snd ),
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.fm_snd_right (),
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.snd_right ( snd ),
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.snd_left (),
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.snd_sample ( snd_sample )
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);
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endmodule // jt03
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