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61 lines
1.2 KiB
Verilog
61 lines
1.2 KiB
Verilog
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// This module generates video for DAC
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// (c)2015 TSL
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module video_out
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(
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// clocks
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input wire clk, c3,
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// video controls
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input wire tv_blank,
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input wire [1:0] plex_sel_in,
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// mode controls
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input wire tv_hires,
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input wire [3:0] palsel,
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// Z80 pins
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input wire [15:0] cram_data_in,
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input wire [7:0] cram_addr_in,
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input wire cram_we,
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// video data
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input wire [7:0] vplex_in,
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output wire [7:0] vred,
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output wire [7:0] vgrn,
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output wire [7:0] vblu,
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output wire vdac_mode
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);
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reg [7:0] vplex;
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always @(posedge clk) if (c3) vplex <= vplex_in;
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wire [7:0] vdata = tv_hires ? {palsel, plex_sel_in[1] ? vplex[3:0] : vplex[7:4]} : vplex;
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// CRAM
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wire [15:0] vpixel;
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dpram #(.DATAWIDTH(16), .ADDRWIDTH(8), .MEM_INIT_FILE("rtl/video/video_cram.mif")) video_cram
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(
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.clock (clk),
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.address_a(cram_addr_in),
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.data_a (cram_data_in),
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.wren_a (cram_we),
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.address_b(vdata),
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.q_b (vpixel)
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);
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reg blank;
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always @(posedge clk) blank <= tv_blank;
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wire [14:0] vpix = blank ? 15'b0 : vpixel[14:0];
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assign vred = {vpix[14:10], vpix[14:12]};
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assign vgrn = {vpix[ 9: 5], vpix[ 9: 7]};
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assign vblu = {vpix[ 4: 0], vpix[ 4: 2]};
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assign vdac_mode = vpixel[15];
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endmodule
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