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https://github.com/UzixLS/TSConf_MiST.git
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249 lines
7.6 KiB
Verilog
249 lines
7.6 KiB
Verilog
//-----------------------------------------------------------------[18.10.2014]
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// MC146818A REAL-TIME CLOCK PLUS RAM
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//-----------------------------------------------------------------------------
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// V0.1 05.10.2011 Initial version
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// V0.2 06.09.2014 Added General Purpose RAM
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module mc146818a
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(
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input RESET,
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input CLK,
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input ENA,
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input CS,
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input [64:0] RTC,
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input [31:0] CMOSCfg,
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input [7:0] KEYSCANCODE,
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input WR,
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input [7:0] A,
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input [7:0] DI,
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output [7:0] DO
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);
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reg [18:0] pre_scaler =0;
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reg [1:0] leap_reg =0;
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reg [7:0] seconds_reg =0; // 00
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reg [7:0] seconds_alarm_reg =0; // 01
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reg [7:0] minutes_reg =0; // 02
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reg [7:0] minutes_alarm_reg = 0;// 03
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reg [7:0] hours_reg =0; // 04
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reg [7:0] hours_alarm_reg ='hff;// 05
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reg [7:0] weeks_reg = 1; // 06
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reg [7:0] days_reg = 1; // 07
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reg [7:0] month_reg = 1; // 08
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reg [7:0] year_reg = 0; // 09
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reg [7:0] a_reg; // 0A
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reg [7:0] b_reg = 8'b00000010; // 0B
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reg [7:0] c_reg; // 0C
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wire [7:0] CMOS_Dout;
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reg [7:0] Dout;
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assign DO = Dout;
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always @(*) begin
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case (A[7:0])
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8'h00 : Dout <= seconds_reg;
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8'h01 : Dout <= seconds_alarm_reg;
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8'h02 : Dout <= minutes_reg;
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8'h03 : Dout <= minutes_alarm_reg;
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8'h04 : Dout <= hours_reg;
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8'h05 : Dout <= hours_alarm_reg;
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8'h06 : Dout <= weeks_reg;
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8'h07 : Dout <= days_reg;
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8'h08 : Dout <= month_reg;
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8'h09 : Dout <= year_reg;
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8'h0a : Dout <= a_reg;
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8'h0b : Dout <= b_reg;
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8'h0c : Dout <= c_reg;
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8'h0d : Dout <= 8'b10000000;
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8'hb1 : Dout <= CMOSCfg[7:6]; // CPU Speed
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8'hb2 : Dout <= 0; // Boot device
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8'hb3 : Dout <= CMOSCfg[8]; // CPU Cache
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8'hb4 : Dout <= CMOSCfg[13:11]; // F11
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8'hb5 : Dout <= CMOSCfg[15:14]; // F11 bank
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8'hb6 : Dout <= CMOSCfg[18:16]; // Shift+F11
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8'hb7 : Dout <= CMOSCfg[20:19]; // Shift+F11 bank
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8'hb8 : Dout <= CMOSCfg[10:9]; // #7FFD
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8'hb9 : Dout <= CMOSCfg[23:21]; // ZX Palette
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8'hba : Dout <= CMOSCfg[24]; // NGS Reset
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8'hbb : Dout <= CMOSCfg[27:25]; // INT offset
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8'hf0 : Dout <= KEYSCANCODE;
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default: Dout <= CMOS_Dout;
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endcase
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end
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always @(posedge CLK) begin
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reg flg;
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flg <= RTC[64];
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if (flg != RTC[64]) begin
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seconds_reg <= RTC[7:0];
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minutes_reg <= RTC[15:8];
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hours_reg <= RTC[23:16];
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days_reg <= RTC[31:24];
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month_reg <= RTC[39:32];
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year_reg <= RTC[47:40];
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weeks_reg <= RTC[55:48] + 1'b1;
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b_reg <= 8'b00000010;
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end
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if (RESET) b_reg <= 8'b00000010;
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else if (WR & CS) begin
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/*
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case (A[7:0])
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0 : seconds_reg <= DI;
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1 : seconds_alarm_reg <= DI;
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2 : minutes_reg <= DI;
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3 : minutes_alarm_reg <= DI;
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4 : hours_reg <= DI;
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5 : hours_alarm_reg <= DI;
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6 : weeks_reg <= DI;
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7 : days_reg <= DI;
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8 : month_reg <= DI;
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9 : year_reg <= DI;
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11 : begin
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b_reg <= DI;
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if (b_reg[2] == 1'b0) begin // BCD to BIN convertion
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if (DI[4] == 1'b0) leap_reg <= DI[1:0];
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else leap_reg <= {~DI[1], DI[0]};
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end
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else begin
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leap_reg <= DI[1:0];
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end
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end
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endcase
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*/
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end
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if (RESET) begin
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a_reg <= 8'b00100110;
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c_reg <= 0;
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end
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else if (~b_reg[7] & ENA) begin
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if (pre_scaler) begin
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pre_scaler <= pre_scaler - 1'd1;
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a_reg[7] <= 0;
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end
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else begin
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pre_scaler <= 437500; //(0.4375MHz)
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a_reg[7] <= 1;
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c_reg[4] <= 1;
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// alarm
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if ((seconds_reg == seconds_alarm_reg) && (minutes_reg == minutes_alarm_reg) && (hours_reg == hours_alarm_reg)) c_reg[5] <= 1'b1;
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if (~b_reg[2]) begin
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// DM binary-coded-decimal (BCD) data mode
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if (seconds_reg[3:0] != 9) seconds_reg[3:0] <= seconds_reg[3:0] + 1'd1;
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else begin
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seconds_reg[3:0] <= 0;
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if (seconds_reg[6:4] != 5) seconds_reg[6:4] <= seconds_reg[6:4] + 1'd1;
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else begin
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seconds_reg[6:4] <= 0;
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if (minutes_reg[3:0] != 9) minutes_reg[3:0] <= minutes_reg[3:0] + 1'd1;
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else begin
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minutes_reg[3:0] <= 0;
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if (minutes_reg[6:4] != 5) minutes_reg[6:4] <= minutes_reg[6:4] + 1'd1;
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else begin
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minutes_reg[6:4] <= 0;
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if (hours_reg[3:0] == 9) begin
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hours_reg[3:0] <= 0;
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hours_reg[5:4] <= hours_reg[5:4] + 1'd1;
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end
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else if ({b_reg[1], hours_reg[7], hours_reg[4:0]} == 7'b0010010) begin
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hours_reg[4:0] <= 1;
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hours_reg[7] <= ~hours_reg[7];
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end
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else if (({b_reg[1], hours_reg[7], hours_reg[4:0]} != 7'b0110010) &&
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({b_reg[1], hours_reg[5:0]} != 7'b1100011)) hours_reg[3:0] <= hours_reg[3:0] + 1'd1;
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else begin
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if (~b_reg[1]) hours_reg[7:0] <= 1;
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else hours_reg[5:0] <= 0;
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if (weeks_reg[2:0] != 7) weeks_reg[2:0] <= weeks_reg[2:0] + 1'd1;
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else weeks_reg[2:0] <= 1;
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if (({month_reg, days_reg, leap_reg} == {16'h0228, 2'b01}) ||
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({month_reg, days_reg, leap_reg} == {16'h0228, 2'b10}) ||
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({month_reg, days_reg, leap_reg} == {16'h0228, 2'b11}) ||
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({month_reg, days_reg, leap_reg} == {16'h0229, 2'b00}) ||
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({month_reg, days_reg} == 16'h0430) ||
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({month_reg, days_reg} == 16'h0630) ||
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({month_reg, days_reg} == 16'h0930) ||
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({month_reg, days_reg} == 16'h1130) ||
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(days_reg == 8'h31)) begin
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days_reg[5:0] <= 1;
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if (month_reg[3:0] == 9) month_reg[4:0] <= 'h10;
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else if (month_reg[4:0] != 'h12) month_reg[3:0] <= month_reg[3:0] + 1'd1;
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else begin
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month_reg[4:0] <= 1;
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leap_reg[1:0] <= leap_reg[1:0] + 1'd1;
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if (year_reg[3:0] != 9) year_reg[3:0] <= year_reg[3:0] + 1'd1;
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else begin
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year_reg[3:0] <= 0;
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if (year_reg[7:4] != 9) year_reg[7:4] <= year_reg[7:4] + 1'd1;
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else year_reg[7:4] <= 0;
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end
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end
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end
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else if (days_reg[3:0] != 9) days_reg[3:0] <= days_reg[3:0] + 1'd1;
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else begin
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days_reg[3:0] <= 0;
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days_reg[5:4] <= days_reg[5:4] + 1'd1;
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end
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end
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end
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end
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end
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end
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end else begin
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// DM binary data mode
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if (seconds_reg != 8'h3B) seconds_reg <= seconds_reg + 1'd1;
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else begin
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seconds_reg <= 0;
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if (minutes_reg != 8'h3B) minutes_reg <= minutes_reg + 1'd1;
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else begin
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minutes_reg <= 0;
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if ({b_reg[1], hours_reg[7], hours_reg[3:0]} == 6'b001100) hours_reg[7:0] <= 8'b10000001;
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else if (({b_reg[1], hours_reg[7], hours_reg[3:0]} != 6'b011100) & ({b_reg[1], hours_reg[4:0]} != 6'b110111)) hours_reg[4:0] <= hours_reg[4:0] + 1'd1;
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else begin
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if (b_reg[1] == 1'b0) hours_reg[7:0] <= 1;
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else hours_reg <= 0;
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if (weeks_reg != 7) weeks_reg <= weeks_reg + 1'd1;
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else weeks_reg <= 1; // Sunday = 1
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if (({month_reg, days_reg, leap_reg} == {16'h021C, 2'b01}) | ({month_reg, days_reg, leap_reg} == {16'h021C, 2'b10}) | ({month_reg, days_reg, leap_reg} == {16'h021C, 2'b11}) | ({month_reg, days_reg, leap_reg} == {16'h021D, 2'b00}) | ({month_reg, days_reg} == 16'h041E) | ({month_reg, days_reg} == 16'h061E) | ({month_reg, days_reg} == 16'h091E) | ({month_reg, days_reg} == 16'h0B1E) | (days_reg == 8'h1F)) begin
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days_reg <= 1;
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if (month_reg != 8'h0C) month_reg <= month_reg + 1'd1;
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else begin
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month_reg <= 1;
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leap_reg[1:0] <= leap_reg[1:0] + 1'd1;
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if (year_reg != 8'h63) year_reg <= year_reg + 1'd1;
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else year_reg <= 0;
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end
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end else days_reg <= days_reg + 1'd1;
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end
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end
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end
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end
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end
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end
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end
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// 50 Bytes of General Purpose RAM
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dpram #(.DATAWIDTH(8), .ADDRWIDTH(8), .MEM_INIT_FILE("rtl/rtc/CMOS.mif")) CMOS
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(
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.clock (CLK),
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.address_a (A),
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.data_a (DI),
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.wren_a (WR & CS),
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.q_a (CMOS_Dout)
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);
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endmodule
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