mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
5022d16b77
Code to check: 10 out 61431, 128 20 out 57335, 0 30 print in 49143; 40 print " "; 50 goto 30
747 lines
20 KiB
Verilog
747 lines
20 KiB
Verilog
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// PentEvo project (c) NedoPC 2008-2010
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`include "tune.v"
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module zports
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(
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input wire zclk, // z80 clock
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input wire clk,
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input wire [ 7:0] din,
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output reg [ 7:0] dout,
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output wire dataout,
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input wire [15:0] a,
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input wire rst, // system reset
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input wire opfetch,
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input wire rd,
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input wire wr,
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input wire rdwr,
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input wire iorq,
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input wire iorq_s,
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input wire iord,
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input wire iord_s,
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input wire iowr,
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input wire iowr_s,
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input wire iordwr,
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input wire iordwr_s,
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output wire porthit, // when internal port hit occurs, this is 1, else 0; used for iorq1_n iorq2_n on zxbus
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output wire external_port, // asserts for AY and VG93 accesses
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output wire zborder_wr,
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output wire border_wr,
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output wire zvpage_wr,
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output wire vpage_wr,
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output wire vconf_wr,
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output wire gx_offsl_wr,
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output wire gx_offsh_wr,
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output wire gy_offsl_wr,
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output wire gy_offsh_wr,
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output wire t0x_offsl_wr,
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output wire t0x_offsh_wr,
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output wire t0y_offsl_wr,
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output wire t0y_offsh_wr,
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output wire t1x_offsl_wr,
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output wire t1x_offsh_wr,
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output wire t1y_offsl_wr,
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output wire t1y_offsh_wr,
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output wire tsconf_wr,
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output wire palsel_wr,
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output wire tmpage_wr,
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output wire t0gpage_wr,
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output wire t1gpage_wr,
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output wire sgpage_wr,
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output wire hint_beg_wr,
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output wire vint_begl_wr,
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output wire vint_begh_wr,
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output wire [31:0] xt_page,
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output reg [4:0] fmaddr,
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input wire regs_we,
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output reg [7:0] sysconf,
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output reg [7:0] memconf,
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output reg [3:0] cacheconf,
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input wire cfg_floppy_swap,
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output reg [7:0] fddvirt,
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`ifdef FDR
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output reg fdr_en,
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output wire fdr_cnt_lat,
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input wire [18:0] fdr_cnt,
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output wire [9:0] dmaport_wr,
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`else
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output wire [8:0] dmaport_wr,
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`endif
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input wire dma_act,
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output reg [1:0] dmawpdev,
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output reg [7:0] intmask,
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input wire dos,
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input wire vdos,
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output wire vdos_on,
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output wire vdos_off,
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output wire ay_bdir,
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output wire ay_bc1,
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output wire covox_wr,
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output wire beeper_wr,
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input wire tape_read,
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`ifdef IDE_HDD
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// IDE interface
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input wire [15:0] ide_in,
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output wire [15:0] ide_out,
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output wire ide_cs0_n,
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output wire ide_cs1_n,
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output wire ide_req,
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input wire ide_stb,
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input wire ide_ready,
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output reg ide_stall,
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`endif
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input wire [ 4:0] keys_in, // keys (port FE)
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input wire [ 7:0] mus_in, // mouse (xxDF)
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`ifdef KEMPSTON_8BIT
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input wire [ 7:0] kj_in,
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`else
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input wire [ 4:0] kj_in,
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`endif
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input wire vg_intrq,
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input wire vg_drq, // from vg93 module - drq + irq read
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output wire vg_cs_n,
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output wire vg_wrFF,
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output wire [1:0] drive_sel, // disk drive selection
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// SPI
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output wire sdcs_n,
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output wire sd2cs_n,
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`ifdef IDE_VDAC2
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output wire ftcs_n,
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`ifdef ESP32_SPI
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output wire espcs_n,
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`endif
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`endif
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output reg spi_mode,
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output wire sd_start,
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output wire [ 7:0] sd_datain,
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input wire [ 7:0] sd_dataout,
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// WAIT-ports related
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output reg [ 7:0] wait_addr,
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output wire wait_start_gluclock, // begin wait from some ports
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output wire wait_start_comport, //
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output reg [ 7:0] wait_write,
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input wire [ 7:0] wait_read
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);
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//#nnAF
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localparam VCONF = 8'h00;
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localparam VPAGE = 8'h01;
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localparam GXOFFSL = 8'h02;
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localparam GXOFFSH = 8'h03;
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localparam GYOFFSL = 8'h04;
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localparam GYOFFSH = 8'h05;
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localparam TSCONF = 8'h06;
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localparam PALSEL = 8'h07;
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localparam XBORDER = 8'h0F;
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localparam T0XOFFSL = 8'h40;
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localparam T0XOFFSH = 8'h41;
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localparam T0YOFFSL = 8'h42;
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localparam T0YOFFSH = 8'h43;
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localparam T1XOFFSL = 8'h44;
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localparam T1XOFFSH = 8'h45;
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localparam T1YOFFSL = 8'h46;
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localparam T1YOFFSH = 8'h47;
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localparam RAMPAGE = 8'h10; // this covers #10-#13
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localparam FMADDR = 8'h15;
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localparam TMPAGE = 8'h16;
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localparam T0GPAGE = 8'h17;
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localparam T1GPAGE = 8'h18;
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localparam SGPAGE = 8'h19;
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localparam DMASADDRL = 8'h1A;
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localparam DMASADDRH = 8'h1B;
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localparam DMASADDRX = 8'h1C;
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localparam DMADADDRL = 8'h1D;
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localparam DMADADDRH = 8'h1E;
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localparam DMADADDRX = 8'h1F;
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localparam SYSCONF = 8'h20;
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localparam MEMCONF = 8'h21;
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localparam HSINT = 8'h22;
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localparam VSINTL = 8'h23;
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localparam VSINTH = 8'h24;
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localparam DMAWPD = 8'h25;
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localparam DMALEN = 8'h26;
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localparam DMACTRL = 8'h27;
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localparam DMANUM = 8'h28;
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localparam FDDVIRT = 8'h29;
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localparam INTMASK = 8'h2A;
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localparam CACHECONF = 8'h2B;
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localparam DMAWPA = 8'h2D;
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localparam XSTAT = 8'h00;
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localparam DMASTAT = 8'h27;
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`ifdef FDR
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localparam DMANUMH = 8'h2C;
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localparam FRCTRL = 8'h30;
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localparam FRCNT0 = 8'h30;
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localparam FRCNT1 = 8'h31;
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localparam FRCNT2 = 8'h32;
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`endif
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`ifdef FDR
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localparam FDR_VER = 1'b1;
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`else
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localparam FDR_VER = 1'b0;
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`endif
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`ifdef IDE_VDAC
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localparam VDAC_VER = 3'h3;
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`elsif IDE_VDAC2
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localparam VDAC_VER = 3'h7;
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`else
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localparam VDAC_VER = 3'h0;
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`endif
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localparam PORTFE = 8'hFE;
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localparam PORTFD = 8'hFD;
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localparam PORTXT = 8'hAF;
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localparam PORTF7 = 8'hF7;
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localparam COVOX = 8'hFB;
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`ifdef IDE_HDD
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localparam NIDE10 = 8'h10;
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localparam NIDE11 = 8'h11;
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localparam NIDE30 = 8'h30;
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localparam NIDE50 = 8'h50;
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localparam NIDE70 = 8'h70;
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localparam NIDE90 = 8'h90;
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localparam NIDEB0 = 8'hB0;
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localparam NIDED0 = 8'hD0;
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localparam NIDEF0 = 8'hF0;
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localparam NIDE08 = 8'h08;
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localparam NIDE28 = 8'h28;
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localparam NIDE48 = 8'h48;
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localparam NIDE68 = 8'h68;
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localparam NIDE88 = 8'h88;
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localparam NIDEA8 = 8'hA8;
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localparam NIDEC8 = 8'hC8;
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localparam NIDEE8 = 8'hE8;
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`endif
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localparam VGCOM = 8'h1F;
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localparam VGTRK = 8'h3F;
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localparam VGSEC = 8'h5F;
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localparam VGDAT = 8'h7F;
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localparam VGSYS = 8'hFF;
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localparam KJOY = 8'h1F;
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localparam KMOUSE = 8'hDF;
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localparam SDCFG = 8'h77;
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localparam SDDAT = 8'h57;
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localparam COMPORT = 8'hEF; // F8EF..FFEF - rs232 ports
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reg [3:0] spi_cs_n;
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reg pwr_up_reg;
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reg [7:0] rampage[0:3];
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wire gluclock_on;
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wire p7ffd_wr;
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assign sdcs_n = spi_cs_n[0];
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assign sd2cs_n = spi_cs_n[2];
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`ifdef IDE_VDAC2
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assign ftcs_n = spi_cs_n[1];
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`ifdef ESP32_SPI
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assign espcs_n = spi_cs_n[3];
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`endif
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`endif
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wire open_vg;
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wire [7:0] loa = a[7:0];
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wire [7:0] hoa = regs_we ? a[7:0] : a[15:8];
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wire vg_port = (loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT);
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wire vgsys_port = (loa==VGSYS);
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assign porthit = ((loa==PORTFE) || (loa==PORTXT) || (loa==PORTFD) || (loa==COVOX)) || ((loa==PORTF7) && !dos)
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`ifdef IDE_HDD
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|| ide_all
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`endif
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|| ((vg_port || vgsys_port) && (dos || open_vg)) || ((loa==KJOY) && !dos && !open_vg) || (loa==KMOUSE) || ((loa==SDCFG) || (loa==SDDAT)) || (loa==COMPORT);
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`ifdef IDE_HDD
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wire ide_all = ide_even || ide_port11;
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wire ide_even = (loa[2:0] == 3'b000) && (loa[3] != loa[4]); // even ports
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wire ide_port11 = (loa==NIDE11); // 11
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wire ide_port10 = (loa==NIDE10); // 10
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wire ide_portc8 = (loa==NIDEC8); // C8
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`endif
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assign external_port = ((loa==PORTFD) && a[15]) // AY
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|| (((loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT)) && (dos || open_vg));
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assign dataout = porthit && iord && (~external_port);
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// zclk-synchronous strobes
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reg iowr_reg;
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reg iord_reg;
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reg port_wr;
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reg port_rd;
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always @(posedge zclk)
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begin
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iowr_reg <= iowr;
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iord_reg <= iord;
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if (!iowr_reg && iowr)
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port_wr <= 1'b1;
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else
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port_wr <= 1'b0;
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if (!iord_reg && iord)
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port_rd <= 1'b1;
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else
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port_rd <= 1'b0;
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end
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// reading ports
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always @*
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begin
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case (loa)
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PORTFE:
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dout = {1'b1, tape_read, 1'b1, keys_in};
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`ifdef IDE_HDD
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NIDE10,NIDE30,NIDE50,NIDE70,NIDE90,NIDEB0,NIDED0,NIDEF0,NIDE08,NIDE28,NIDE48,NIDE68,NIDE88,NIDEA8,NIDEC8,NIDEE8:
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dout = iderdeven;
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NIDE11:
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dout = iderdodd;
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`endif
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PORTXT:
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begin
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case (hoa)
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XSTAT:
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dout = {1'b0, pwr_up_reg, FDR_VER, 2'b0, VDAC_VER};
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DMASTAT:
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dout = {dma_act, 7'b0};
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RAMPAGE + 8'd2, RAMPAGE + 8'd3:
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dout = rampage[hoa[1:0]];
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`ifdef FDR
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FRCNT0:
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dout = fdr_cnt[7:0];
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FRCNT1:
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dout = fdr_cnt[15:8];
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FRCNT2:
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dout = {5'b0, fdr_cnt[18:16]};
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`endif
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default:
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dout = 8'hFF;
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endcase
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end
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VGSYS:
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dout = {vg_intrq, vg_drq, 6'b111111};
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KJOY:
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`ifdef KEMPSTON_8BIT
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dout = kj_in;
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`else
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dout = {3'b000, kj_in};
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`endif
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KMOUSE:
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dout = mus_in;
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SDCFG:
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dout = 8'h00; // always SD inserted, SD is in R/W mode
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SDDAT:
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dout = sd_dataout;
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PORTF7:
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begin
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if (!a[14] && (a[8] ^ dos) && gluclock_on) // $BFF7 - data i/o
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dout = wait_read;
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// dout = 8'h55;
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else // any other $xxF7 port
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dout = 8'hFF;
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end
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COMPORT:
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begin
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dout = wait_read; // $F8EF..$FFEF
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end
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default:
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dout = 8'hFF;
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endcase
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end
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// power-up
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// This bit is loaded as 1 while FPGA is configured and automatically reset to 0 after STATUS port reading
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reg pwr_up = 1'b1;
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always @(posedge clk)
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if (iord_s & (loa == PORTXT) & (hoa == XSTAT))
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begin
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pwr_up_reg <= pwr_up;
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pwr_up <= 1'b0;
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end
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wire portfe_wr = (loa==PORTFE) && iowr_s;
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assign beeper_wr = portfe_wr;
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assign covox_wr = (loa==COVOX) && iowr_s;
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wire portxt_wr = ((loa==PORTXT) && iowr_s) || regs_we;
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wire portxt_rd = (loa==PORTXT) && iord_s;
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assign xt_page = {rampage[3], rampage[2], rampage[1], rampage[0]};
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// writing ports
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assign dmaport_wr[0] = portxt_wr && (hoa == DMASADDRL);
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assign dmaport_wr[1] = portxt_wr && (hoa == DMASADDRH);
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assign dmaport_wr[2] = portxt_wr && (hoa == DMASADDRX);
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assign dmaport_wr[3] = portxt_wr && (hoa == DMADADDRL);
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assign dmaport_wr[4] = portxt_wr && (hoa == DMADADDRH);
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assign dmaport_wr[5] = portxt_wr && (hoa == DMADADDRX);
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assign dmaport_wr[6] = portxt_wr && (hoa == DMALEN);
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assign dmaport_wr[7] = portxt_wr && (hoa == DMACTRL);
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assign dmaport_wr[8] = portxt_wr && (hoa == DMANUM);
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`ifdef FDR
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assign dmaport_wr[9] = portxt_wr && (hoa == DMANUMH);
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`endif
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assign zborder_wr = portfe_wr;
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assign border_wr = (portxt_wr && (hoa == XBORDER));
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assign zvpage_wr = p7ffd_wr;
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assign vpage_wr = (portxt_wr && (hoa == VPAGE ));
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assign vconf_wr = (portxt_wr && (hoa == VCONF ));
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assign gx_offsl_wr = (portxt_wr && (hoa == GXOFFSL));
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assign gx_offsh_wr = (portxt_wr && (hoa == GXOFFSH));
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assign gy_offsl_wr = (portxt_wr && (hoa == GYOFFSL));
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assign gy_offsh_wr = (portxt_wr && (hoa == GYOFFSH));
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assign t0x_offsl_wr = (portxt_wr && (hoa == T0XOFFSL));
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assign t0x_offsh_wr = (portxt_wr && (hoa == T0XOFFSH));
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assign t0y_offsl_wr = (portxt_wr && (hoa == T0YOFFSL));
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assign t0y_offsh_wr = (portxt_wr && (hoa == T0YOFFSH));
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assign t1x_offsl_wr = (portxt_wr && (hoa == T1XOFFSL));
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assign t1x_offsh_wr = (portxt_wr && (hoa == T1XOFFSH));
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assign t1y_offsl_wr = (portxt_wr && (hoa == T1YOFFSL));
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assign t1y_offsh_wr = (portxt_wr && (hoa == T1YOFFSH));
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assign tsconf_wr = (portxt_wr && (hoa == TSCONF));
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assign palsel_wr = (portxt_wr && (hoa == PALSEL));
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assign tmpage_wr = (portxt_wr && (hoa == TMPAGE));
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assign t0gpage_wr = (portxt_wr && (hoa == T0GPAGE));
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assign t1gpage_wr = (portxt_wr && (hoa == T1GPAGE));
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assign sgpage_wr = (portxt_wr && (hoa == SGPAGE));
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assign hint_beg_wr = (portxt_wr && (hoa == HSINT ));
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assign vint_begl_wr = (portxt_wr && (hoa == VSINTL));
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assign vint_begh_wr = (portxt_wr && (hoa == VSINTH));
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`ifdef FDR
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assign fdr_cnt_lat = (portxt_rd && (hoa == FRCNT0));
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`endif
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reg m1_lock128;
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wire lock128_2 = memconf[7:6] == 2'b10; // mode 2
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wire lock128_3 = memconf[7:6] == 2'b11; // mode 3
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wire lock128 = lock128_3 ? 1'b0 : (lock128_2 ? m1_lock128 : memconf[6]);
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always @(posedge clk) if (opfetch)
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m1_lock128 <= !(din[7] ^ din[6]);
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|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
begin
|
|
fmaddr[4] <= 1'b0;
|
|
intmask <= 8'b1;
|
|
fddvirt <= 8'b0;
|
|
sysconf <= 8'h00; // 3.5 MHz
|
|
memconf <= 8'h04; // no map
|
|
cacheconf <= 4'h0; // no cache
|
|
|
|
rampage[0] <= 8'h00;
|
|
rampage[1] <= 8'h05;
|
|
rampage[2] <= 8'h02;
|
|
rampage[3] <= 8'h00;
|
|
|
|
`ifdef FDR
|
|
fdr_en <= 1'b0;
|
|
`endif
|
|
end
|
|
else // if (rst)
|
|
begin
|
|
if (p7ffd_wr)
|
|
begin
|
|
memconf[0] <= din[4];
|
|
rampage[3] <= {2'b0, lock128_3 ? {din[5], din[7:6]} : ({1'b0, lock128 ? 2'b0 : din[7:6]}), din[2:0]};
|
|
end
|
|
|
|
else if (portxt_wr)
|
|
begin
|
|
if (hoa[7:2] == RAMPAGE[7:2])
|
|
rampage[hoa[1:0]] <= din;
|
|
|
|
if (hoa == FMADDR)
|
|
fmaddr <= din[4:0];
|
|
|
|
if (hoa == SYSCONF)
|
|
begin
|
|
sysconf <= din;
|
|
cacheconf <= {4{din[2]}};
|
|
end
|
|
|
|
if (hoa == DMAWPD)
|
|
dmawpdev <= din[1:0];
|
|
|
|
if (hoa == CACHECONF)
|
|
cacheconf <= din[3:0];
|
|
|
|
if (hoa == MEMCONF)
|
|
memconf <= din;
|
|
|
|
if (hoa == FDDVIRT)
|
|
fddvirt <= din;
|
|
|
|
`ifdef FDR
|
|
if (hoa == FRCTRL)
|
|
fdr_en <= din[0];
|
|
`endif
|
|
|
|
if (hoa == INTMASK)
|
|
intmask <= din;
|
|
end
|
|
end
|
|
|
|
// 7FFD port
|
|
reg lock48;
|
|
|
|
assign p7ffd_wr = !a[15] && (loa==PORTFD) && iowr_s && !lock48;
|
|
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
lock48 <= 1'b0;
|
|
else if (p7ffd_wr && !lock128_3)
|
|
lock48 <= din[5];
|
|
|
|
// AY control
|
|
wire ay_hit = (loa==PORTFD) & a[15];
|
|
assign ay_bc1 = ay_hit & a[14] & iordwr;
|
|
assign ay_bdir = ay_hit & iowr;
|
|
|
|
// VG93
|
|
reg [1:0] drive_sel_raw;
|
|
|
|
wire [3:0] fddvrt = fddvirt[3:0];
|
|
wire virt_vg = fddvrt[drive_sel_raw];
|
|
assign open_vg = fddvirt[7];
|
|
assign drive_sel = {drive_sel_raw[1], drive_sel_raw[0] ^ cfg_floppy_swap};
|
|
|
|
wire vg_wen = (dos || open_vg) && !vdos && !virt_vg;
|
|
assign vg_cs_n = !(iordwr && vg_port && vg_wen);
|
|
assign vg_wrFF = iowr_s && vgsys_port && vg_wen;
|
|
wire vg_wrDS = iowr_s && vgsys_port && (dos || open_vg);
|
|
|
|
assign vdos_on = iordwr_s && (vg_port || vgsys_port) && dos && !vdos && virt_vg;
|
|
assign vdos_off = iordwr_s && vg_port && vdos;
|
|
|
|
// write drive number
|
|
always @(posedge clk)
|
|
if (vg_wrDS)
|
|
drive_sel_raw <= din;
|
|
|
|
// SD card (Z-controller compatible)
|
|
wire sdcfg_wr;
|
|
wire sddat_wr;
|
|
wire sddat_rd;
|
|
|
|
assign sdcfg_wr = (loa==SDCFG) && iowr_s;
|
|
assign sddat_wr = (loa==SDDAT) && iowr_s;
|
|
assign sddat_rd = (loa==SDDAT) && iord_s;
|
|
|
|
// SDCFG write - sdcs_n control
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
begin
|
|
spi_cs_n <= 4'b1111;
|
|
spi_mode <= 1'b0;
|
|
end
|
|
else if (sdcfg_wr)
|
|
begin
|
|
spi_cs_n <= {~din[4:2], din[1]};
|
|
// spi_mode <= din[7];
|
|
end
|
|
|
|
// start signal for SPI module with resyncing to fclk
|
|
assign sd_start = sddat_wr || sddat_rd;
|
|
|
|
// data for SPI module
|
|
assign sd_datain = wr ? din : 8'hFF;
|
|
|
|
// xxF7
|
|
wire portf7_wr = ((loa==PORTF7) && (a[8]==1'b1) && port_wr && (!dos || vdos));
|
|
wire portf7_rd = ((loa==PORTF7) && (a[8]==1'b1) && port_rd && (!dos || vdos));
|
|
|
|
// EFF7 port
|
|
reg [7:0] peff7;
|
|
always @(posedge clk or posedge rst)
|
|
if (rst)
|
|
peff7 <= 8'h00;
|
|
else if (!a[12] && portf7_wr && !dos) // #EEF7 in dos is not accessible
|
|
peff7 <= din;
|
|
|
|
// gluclock ports
|
|
assign gluclock_on = peff7[7] || dos; // in dos mode EEF7 is not accessible, gluclock access is ON in dos mode.
|
|
|
|
// comports
|
|
wire comport_wr = ((loa == COMPORT) && port_wr);
|
|
wire comport_rd = ((loa == COMPORT) && port_rd);
|
|
|
|
// write to wait registers
|
|
always @(posedge zclk)
|
|
begin
|
|
// gluclocks
|
|
if (gluclock_on && portf7_wr)
|
|
begin
|
|
if (!a[14]) // $BFF7 - data reg
|
|
wait_write <= din;
|
|
|
|
if (!a[13]) // $DFF7 - addr reg
|
|
wait_addr <= din;
|
|
end
|
|
|
|
// com ports
|
|
if (comport_wr) // $xxEF
|
|
wait_write <= din;
|
|
|
|
if (comport_wr || comport_rd)
|
|
wait_addr <= a[15:8];
|
|
|
|
if (portxt_wr && (hoa == DMAWPA))
|
|
wait_addr <= din;
|
|
end
|
|
|
|
// wait from wait registers
|
|
assign wait_start_gluclock = (gluclock_on && !a[14] && (portf7_rd || portf7_wr)); // $BFF7 - gluclock r/w
|
|
assign wait_start_comport = (comport_rd || comport_wr);
|
|
|
|
`ifdef IDE_HDD
|
|
// IDE ports
|
|
// do NOT generate IDE write, if neither of ide_wrhi|lo latches set and writing to NIDE10
|
|
wire ide_cs0 = ide_even && !ide_portc8;
|
|
wire ide_cs1 = ide_portc8;
|
|
wire ide_rd = rd && !(ide_rd_latch && ide_port10);
|
|
wire ide_wr = wr && !(!ide_wrlo_latch && !ide_wrhi_latch && ide_port10);
|
|
assign ide_req = iorq_s && ide_even && (ide_rd || ide_wr);
|
|
assign ide_cs0_n = !ide_cs0;
|
|
assign ide_cs1_n = !ide_cs1;
|
|
|
|
always @(posedge clk)
|
|
if (ide_req)
|
|
ide_stall <= 1'b1;
|
|
else if (ide_ready)
|
|
ide_stall <= 1'b0;
|
|
|
|
// control read & write triggers, which allow nemo-divide mod to work.
|
|
// read trigger:
|
|
reg ide_rd_trig; // nemo-divide read trigger
|
|
always @(posedge zclk)
|
|
begin
|
|
if (ide_port10 && port_rd && !ide_rd_trig)
|
|
ide_rd_trig <= 1'b1;
|
|
else if (ide_all && (port_rd || port_wr))
|
|
ide_rd_trig <= 1'b0;
|
|
end
|
|
|
|
// two triggers for write sequence
|
|
reg ide_wrlo_trig, ide_wrhi_trig; // nemo-divide write triggers
|
|
always @(posedge zclk)
|
|
if (ide_all && (port_rd || port_wr))
|
|
begin
|
|
if (ide_port11 && port_wr)
|
|
ide_wrhi_trig <= 1'b1;
|
|
else
|
|
ide_wrhi_trig <= 1'b0;
|
|
|
|
if (ide_port10 && port_wr && !ide_wrhi_trig && !ide_wrlo_trig)
|
|
ide_wrlo_trig <= 1'b1;
|
|
else
|
|
ide_wrlo_trig <= 1'b0;
|
|
end
|
|
|
|
// normal read: #10(low), #11(high)
|
|
// divide read: #10(low), #10(high)
|
|
//
|
|
// normal write: #11(high), #10(low)
|
|
// divide write: #10(low), #10(high)
|
|
|
|
reg [15:0] idewrreg; // write register, either low or high part is pre-written here,
|
|
// while other part is out directly from Z80 bus
|
|
always @(posedge zclk)
|
|
begin
|
|
if (port_wr && ide_port11)
|
|
idewrreg[15:8] <= din;
|
|
|
|
if (port_wr && ide_port10 && !ide_wrlo_trig)
|
|
idewrreg[ 7:0] <= din;
|
|
end
|
|
|
|
// generate read cycles for IDE as usual, except for reading #10
|
|
// instead of #11 for high byte (nemo-divide). I use additional latch
|
|
// since 'ide_rd_trig' clears during second Z80 IO read cycle to #10
|
|
reg ide_rd_latch; // to save state of trigger during read cycle
|
|
always @*
|
|
if (!rd)
|
|
ide_rd_latch <= ide_rd_trig;
|
|
|
|
reg ide_wrlo_latch, ide_wrhi_latch; // save state during write cycles
|
|
always @*
|
|
if (!wr)
|
|
begin
|
|
ide_wrlo_latch <= ide_wrlo_trig; // same for write triggers
|
|
ide_wrhi_latch <= ide_wrhi_trig;
|
|
end
|
|
|
|
// data read by Z80 from IDE
|
|
wire idein_lo_rd = port_rd && ide_port10 && (!ide_rd_trig); // while high part is remembered here
|
|
wire [7:0] iderdodd = iderdreg[15:8]; // read data from "odd" port (#11)
|
|
wire [7:0] iderdeven = (ide_rd_latch && ide_port10) ? iderdreg[15:8] : iderdreg[7:0]; // to control read data from "even" ide ports (all except #11)
|
|
// wire [7:0] iderdeven = (ide_rd_latch && ide_port10) ? idehiin[7:0] : ide_in[7:0]; // to control read data from "even" ide ports (all except #11)
|
|
|
|
reg [15:0] iderdreg;
|
|
// reg [7:0] idehiin; // IDE high part read register: low part is read directly to Z80 bus,
|
|
always @(posedge clk)
|
|
if (ide_stb)
|
|
iderdreg <= ide_in;
|
|
// if (idein_lo_rd)
|
|
// idehiin <= ide_in[15:8];
|
|
|
|
// data written to IDE from Z80
|
|
wire [7:0] ideout1 = ide_wrhi_latch ? idewrreg[15:8] : din[ 7:0];
|
|
wire [7:0] ideout0 = ide_wrlo_latch ? idewrreg[ 7:0] : din[ 7:0];
|
|
assign ide_out = {ideout1, ideout0};
|
|
`endif
|
|
|
|
endmodule
|