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https://github.com/UzixLS/TSConf_MiST.git
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217 lines
8.0 KiB
VHDL
217 lines
8.0 KiB
VHDL
--
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-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig)
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--
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-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t80/
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--
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-- File history :
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--
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-- v1.0: convert to preudo-asynchronous model with original Z80 timings.
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--
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-- v2.0: rewritten for more precise timings.
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-- support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2.
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--
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-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
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--
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-- v2.2: Interrupt acknowledge cycle has been corrected
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-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
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--
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-- v2.3: Output last used Address during non-bus MCycle seems more correct.
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--
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-- v2.4: Use the fixed WAIT_n in T80.vhd
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.T80_Pack.all;
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entity T80pa is
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generic(
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Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
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);
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port(
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RESET_n : in std_logic;
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CLK : in std_logic;
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CEN_p : in std_logic := '1';
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CEN_n : in std_logic := '1';
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WAIT_n : in std_logic := '1';
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INT_n : in std_logic := '1';
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NMI_n : in std_logic := '1';
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BUSRQ_n : in std_logic := '1';
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M1_n : out std_logic;
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MREQ_n : out std_logic;
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IORQ_n : out std_logic;
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RD_n : out std_logic;
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WR_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
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A : out std_logic_vector(15 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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R800_mode : in std_logic := '0';
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REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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DIRSet : in std_logic := '0';
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DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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);
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end T80pa;
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architecture rtl of T80pa is
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signal IntCycle_n : std_logic;
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signal IntCycleD_n : std_logic_vector(1 downto 0);
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signal IORQ : std_logic;
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signal NoRead : std_logic;
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signal Write : std_logic;
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signal BUSAK : std_logic;
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signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
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signal MCycle : std_logic_vector(2 downto 0);
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signal TState : std_logic_vector(2 downto 0);
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signal CEN_pol : std_logic;
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signal CEN : std_logic;
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signal Wait_s : std_logic;
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begin
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CEN <= CEN_p and not CEN_pol;
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BUSAK_n <= BUSAK;
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u0 : T80
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generic map(
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Mode => Mode,
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IOWait => 1
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)
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port map(
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CEN => CEN,
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M1_n => M1_n,
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IORQ => IORQ,
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NoRead => NoRead,
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Write => Write,
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RFSH_n => RFSH_n,
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HALT_n => HALT_n,
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WAIT_n => Wait_s,
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INT_n => INT_n,
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NMI_n => NMI_n,
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RESET_n => RESET_n,
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BUSRQ_n => BUSRQ_n,
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BUSAK_n => BUSAK,
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CLK_n => CLK,
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A => A,
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DInst => DI, -- valid at beginning of T3
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DI => DI_Reg, -- latched at middle of T3
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DO => DO,
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REG => REG,
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MC => MCycle,
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TS => TState,
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OUT0 => OUT0,
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R800_mode => R800_mode,
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IntCycle_n => IntCycle_n,
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DIRSet => DIRSet,
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DIR => DIR
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);
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process(CLK)
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begin
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if rising_edge(CLK) then
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if RESET_n = '0' then
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WR_n <= '1';
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RD_n <= '1';
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IORQ_n <= '1';
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MREQ_n <= '1';
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DI_Reg <= "00000000";
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CEN_pol <= '0';
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elsif CEN_p = '1' and CEN_pol = '0' then
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CEN_pol <= '1';
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if WAIT_s = '1' or TState /= "010" then
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if MCycle = "001" then
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if TState = "010" then
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IORQ_n <= '1';
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MREQ_n <= '1';
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RD_n <= '1';
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end if;
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else
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if TState = "001" and IORQ = '1' then
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WR_n <= not Write;
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RD_n <= Write;
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IORQ_n <= '0';
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end if;
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end if;
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end if;
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elsif CEN_n = '1' and CEN_pol = '1' then
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Wait_s <= Wait_n;
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CEN_pol <= '0';
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if TState = "011" and BUSAK = '1' then
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DI_Reg <= DI;
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end if;
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if MCycle = "001" then
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if TState = "001" then
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IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
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RD_n <= not IntCycle_n;
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MREQ_n <= not IntCycle_n;
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IORQ_n <= IntCycleD_n(1);
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end if;
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if TState = "011" then
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IntCycleD_n <= "11";
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RD_n <= '1';
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MREQ_n <= '0';
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end if;
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if TState = "100" then
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MREQ_n <= '1';
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end if;
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else
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if NoRead = '0' and IORQ = '0' then
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if TState = "001" then
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RD_n <= Write;
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MREQ_n <= '0';
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end if;
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end if;
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if TState = "010" then
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WR_n <= not Write;
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end if;
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if TState = "011" then
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WR_n <= '1';
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RD_n <= '1';
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IORQ_n <= '1';
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MREQ_n <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end;
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