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https://github.com/UzixLS/TSConf_MiST.git
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154 lines
2.7 KiB
Verilog
154 lines
2.7 KiB
Verilog
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module sdram
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(
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// Memory port
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input clk,
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input cyc,
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input curr_cpu,
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input [1:0] bsel, // Active HI
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input [23:0] A,
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input [15:0] DI,
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output reg [15:0] DO,
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output reg [15:0] DO_cpu,
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input REQ,
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input RNW,
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// SDRAM Pin
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inout reg [15:0] SDRAM_DQ,
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output reg [12:0] SDRAM_A,
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output reg [1:0] SDRAM_BA,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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output SDRAM_CKE,
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output SDRAM_CLK
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);
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reg [2:0] sdr_cmd;
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localparam SdrCmd_xx = 3'b111; // no operation
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localparam SdrCmd_ac = 3'b011; // activate
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localparam SdrCmd_rd = 3'b101; // read
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localparam SdrCmd_wr = 3'b100; // write
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localparam SdrCmd_pr = 3'b010; // precharge all
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localparam SdrCmd_re = 3'b001; // refresh
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localparam SdrCmd_ms = 3'b000; // mode regiser set
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always @(posedge clk) begin
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reg [4:0] state;
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reg rd;
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reg [8:0] col;
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reg [1:0] dqm;
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reg [15:0] data;
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reg [23:0] Ar;
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reg rq;
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sdr_cmd <= SdrCmd_xx;
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data <= SDRAM_DQ;
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SDRAM_DQ <= 16'bZ;
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state <= state + 1'd1;
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case (state)
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// Init
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0: begin
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sdr_cmd <= SdrCmd_pr; // PRECHARGE
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SDRAM_A <= 0;
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SDRAM_BA <= 0;
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end
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// REFRESH
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3,10: begin
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sdr_cmd <= SdrCmd_re;
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end
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// LOAD MODE REGISTER
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17: begin
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sdr_cmd <= SdrCmd_ms;
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SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
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end
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// Idle
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24: begin
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if (rd) begin
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DO <= data;
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if (curr_cpu) DO_cpu <= data;
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end
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state <= state;
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Ar <= A;
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dqm <= RNW ? 2'b00 : ~bsel;
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rd <= 0;
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if(cyc) begin
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rq <= REQ;
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rd <= REQ & RNW;
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state <= state + 1'd1;
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end
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end
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// Start
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25: begin
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if (rq) begin
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{SDRAM_A,SDRAM_BA,col} <= Ar;
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sdr_cmd <= SdrCmd_ac;
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end else begin
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sdr_cmd <= SdrCmd_re;
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state <= 19;
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end
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end
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// Single read/write - with auto precharge
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27: begin
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SDRAM_A <= {dqm, 2'b10, col};
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state <= 21;
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if (rd) sdr_cmd <= SdrCmd_rd;
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else begin
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sdr_cmd <= SdrCmd_wr;
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SDRAM_DQ <= DI;
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state <= 22;
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end
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end
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endcase
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end
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assign SDRAM_CKE = 1;
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assign SDRAM_nCS = 0;
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assign SDRAM_nRAS = sdr_cmd[2];
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assign SDRAM_nCAS = sdr_cmd[1];
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assign SDRAM_nWE = sdr_cmd[0];
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assign SDRAM_DQML = SDRAM_A[11];
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assign SDRAM_DQMH = SDRAM_A[12];
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altddio_out
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#(
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.extend_oe_disable("OFF"),
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.intended_device_family("Cyclone V"),
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.invert_output("OFF"),
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.lpm_hint("UNUSED"),
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.lpm_type("altddio_out"),
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.oe_reg("UNREGISTERED"),
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.power_up_high("OFF"),
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.width(1)
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)
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sdramclk_ddr
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(
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.datain_h(1'b0),
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.datain_l(1'b1),
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.outclock(clk),
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.dataout(SDRAM_CLK),
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.aclr(1'b0),
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.aset(1'b0),
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.oe(1'b1),
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.outclocken(1'b1),
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.sclr(1'b0),
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.sset(1'b0)
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);
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endmodule
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