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73 lines
2.4 KiB
Verilog
73 lines
2.4 KiB
Verilog
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module dpram #(parameter DATAWIDTH=8, ADDRWIDTH=8, NUMWORDS=1<<ADDRWIDTH, MEM_INIT_FILE="")
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(
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input clock,
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input [ADDRWIDTH-1:0] address_a,
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input [DATAWIDTH-1:0] data_a,
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input wren_a,
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output [DATAWIDTH-1:0] q_a,
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input [ADDRWIDTH-1:0] address_b,
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input [DATAWIDTH-1:0] data_b,
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input wren_b,
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output [DATAWIDTH-1:0] q_b
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);
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altsyncram altsyncram_component (
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.address_a (address_a),
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.address_b (address_b),
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.clock0 (clock),
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.data_a (data_a),
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.data_b (data_b),
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.wren_a (wren_a),
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.wren_b (wren_b),
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.q_a (q_a),
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.q_b (q_b),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.eccstatus (),
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.rden_a (1'b1),
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.rden_b (1'b1));
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defparam
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altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.indata_reg_b = "CLOCK0",
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altsyncram_component.numwords_a = NUMWORDS,
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altsyncram_component.numwords_b = NUMWORDS,
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altsyncram_component.widthad_a = ADDRWIDTH,
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altsyncram_component.widthad_b = ADDRWIDTH,
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altsyncram_component.width_a = DATAWIDTH,
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altsyncram_component.width_b = DATAWIDTH,
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altsyncram_component.width_byteena_a = 1,
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altsyncram_component.width_byteena_b = 1,
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altsyncram_component.init_file = MEM_INIT_FILE,
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ";
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endmodule
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