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340 lines
11 KiB
Verilog
340 lines
11 KiB
Verilog
/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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*/
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module jt12_reg(
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input rst,
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input clk,
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input clk_en /* synthesis direct_enable */,
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input [2:0] ch, // channel to update
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input [1:0] op,
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input csm,
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input flag_A,
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input overflow_A,
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// channel udpates
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input [2:0] ch_sel,
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input [7:0] ch_din,
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input up_alg,
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input up_fnumlo,
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// operator updates
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input [7:0] din,
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input up_keyon,
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input up_pms,
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input up_dt1,
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input up_tl,
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input up_ks_ar,
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input up_amen_dr,
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input up_sr,
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input up_sl_rr,
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input up_ssgeg,
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output reg ch6op, // 1 when the operator belongs to CH6
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output reg [2:0] cur_ch,
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output reg [1:0] cur_op,
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// CH3 Effect-mode operation
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input effect,
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input [10:0] fnum_ch3op2,
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input [10:0] fnum_ch3op3,
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input [10:0] fnum_ch3op1,
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input [ 2:0] block_ch3op2,
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input [ 2:0] block_ch3op3,
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input [ 2:0] block_ch3op1,
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input [ 5:0] latch_fnum,
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// Pipeline order
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output reg zero,
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output s1_enters,
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output s2_enters,
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output s3_enters,
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output s4_enters,
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// Operator
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output xuse_prevprev1,
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output xuse_internal,
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output yuse_internal,
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output xuse_prev2,
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output yuse_prev1,
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output yuse_prev2,
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// PG
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output [10:0] fnum_I,
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output [ 2:0] block_I,
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// channel configuration
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output [1:0] rl,
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output reg [2:0] fb_II,
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output [2:0] alg_I,
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// Operator multiplying
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output [ 3:0] mul_II,
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// Operator detuning
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output [ 2:0] dt1_I,
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// EG
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output [4:0] ar_I, // attack rate
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output [4:0] d1r_I, // decay rate
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output [4:0] d2r_I, // sustain rate
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output [3:0] rr_I, // release rate
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output [3:0] sl_I, // sustain level
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output [1:0] ks_II, // key scale
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output ssg_en_I,
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output [2:0] ssg_eg_I,
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output [6:0] tl_IV,
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output [2:0] pms_I,
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output [1:0] ams_IV,
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output amsen_IV,
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// envelope operation
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output keyon_I
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);
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parameter num_ch=6; // Use only 3 (YM2203/YM2610) or 6 (YM2612/YM2608)
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reg [1:0] next_op;
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reg [2:0] next_ch;
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reg last;
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`ifdef SIMULATION
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// These signals need to operate during rst
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// initial state is not relevant (or critical) in real life
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// but we need a clear value during simulation
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// This does not work with NCVERILOG
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initial begin
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cur_op = 2'd0;
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cur_ch = 3'd0;
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next_op = 2'd0;
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next_ch = 3'd1;
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last = 1'b0;
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zero = 1'b1;
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end
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`endif
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assign s1_enters = cur_op == 2'b00;
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assign s3_enters = cur_op == 2'b01;
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assign s2_enters = cur_op == 2'b10;
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assign s4_enters = cur_op == 2'b11;
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wire [4:0] next = { next_op, next_ch };
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wire [4:0] cur = { cur_op, cur_ch };
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wire [2:0] fb_I;
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always @(posedge clk) if( clk_en ) begin
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fb_II <= fb_I;
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ch6op <= next_ch==3'd6;
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end
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// FNUM and BLOCK
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wire [10:0] fnum_I_raw;
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wire [ 2:0] block_I_raw;
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wire effect_on = effect && (cur_ch==3'd2);
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wire effect_on_s1 = effect_on && (cur_op == 2'd0 );
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wire effect_on_s3 = effect_on && (cur_op == 2'd1 );
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wire effect_on_s2 = effect_on && (cur_op == 2'd2 );
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wire noeffect = ~|{effect_on_s1, effect_on_s3, effect_on_s2};
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assign fnum_I = ( {11{effect_on_s1}} & fnum_ch3op1 ) |
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( {11{effect_on_s2}} & fnum_ch3op2 ) |
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( {11{effect_on_s3}} & fnum_ch3op3 ) |
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( {11{noeffect}} & fnum_I_raw );
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assign block_I =( {3{effect_on_s1}} & block_ch3op1 ) |
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( {3{effect_on_s2}} & block_ch3op2 ) |
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( {3{effect_on_s3}} & block_ch3op3 ) |
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( {3{noeffect}} & block_I_raw );
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wire [4:0] req_opch_I = { op, ch };
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wire [4:0] req_opch_II, req_opch_III,
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req_opch_IV, req_opch_V; //, req_opch_VI;
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jt12_sumch #(.num_ch(num_ch)) u_opch_II ( .chin(req_opch_I ), .chout(req_opch_II ) );
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jt12_sumch #(.num_ch(num_ch)) u_opch_III( .chin(req_opch_II ), .chout(req_opch_III) );
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jt12_sumch #(.num_ch(num_ch)) u_opch_IV ( .chin(req_opch_III), .chout(req_opch_IV ) );
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jt12_sumch #(.num_ch(num_ch)) u_opch_V ( .chin(req_opch_IV ), .chout(req_opch_V ) );
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// jt12_sumch #(.num_ch(num_ch)) u_opch_VI ( .chin(req_opch_V ), .chout(req_opch_VI) );
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wire update_op_I = cur == req_opch_I;
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wire update_op_II = cur == req_opch_II;
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// wire update_op_III= cur == req_opch_III;
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wire update_op_IV = cur == req_opch_IV;
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// wire update_op_V = cur == req_opch_V;
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// wire update_op_VI = cur == opch_VI;
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// wire [2:0] op_plus1 = op+2'd1;
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// wire update_op_VII= cur == { op_plus1[1:0], ch };
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// key on/off
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wire [3:0] keyon_op = din[7:4];
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wire [2:0] keyon_ch = din[2:0];
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always @(*) begin
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// next = cur==5'd23 ? 5'd0 : cur +1'b1;
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if( num_ch==6 ) begin
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next_op = cur_ch==3'd6 ? cur_op+1'b1 : cur_op;
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next_ch = cur_ch[1:0]==2'b10 ? cur_ch+2'd2 : cur_ch+1'd1;
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end else begin // 3 channels
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next_op = cur_ch==3'd2 ? cur_op+1'b1 : cur_op;
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next_ch = cur_ch[1:0]==2'b10 ? 3'd0 : cur_ch+1'd1;
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end
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end
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always @(posedge clk) begin : up_counter
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if( clk_en ) begin
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{ cur_op, cur_ch } <= { next_op, next_ch };
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zero <= next == 5'd0;
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end
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end
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`ifndef NOFM
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jt12_kon #(.num_ch(num_ch)) u_kon(
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.rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.keyon_op ( keyon_op ),
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.keyon_ch ( keyon_ch ),
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.next_op ( next_op ),
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.next_ch ( next_ch ),
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.up_keyon ( up_keyon ),
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.csm ( csm ),
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// .flag_A ( flag_A ),
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.overflow_A ( overflow_A),
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.keyon_I ( keyon_I )
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);
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jt12_mod #(.num_ch(num_ch)) u_mod(
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.alg_I ( alg_I ),
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.s1_enters ( s1_enters ),
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.s3_enters ( s3_enters ),
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.s2_enters ( s2_enters ),
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.s4_enters ( s4_enters ),
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.xuse_prevprev1 ( xuse_prevprev1 ),
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.xuse_internal ( xuse_internal ),
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.yuse_internal ( yuse_internal ),
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.xuse_prev2 ( xuse_prev2 ),
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.yuse_prev1 ( yuse_prev1 ),
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.yuse_prev2 ( yuse_prev2 )
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);
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wire [43:0] shift_out;
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generate
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if( num_ch==6 ) begin
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// YM2612 / YM3438: Two CSR.
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wire [43:0] shift_middle;
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jt12_csr u_csr0(
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.rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.din ( din ),
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.shift_in ( shift_out ),
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.shift_out ( shift_middle ),
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.up_tl ( up_tl ),
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.up_dt1 ( up_dt1 ),
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.up_ks_ar ( up_ks_ar ),
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.up_amen_dr ( up_amen_dr ),
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.up_sr ( up_sr ),
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.up_sl_rr ( up_sl_rr ),
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.up_ssgeg ( up_ssgeg ),
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.update_op_I ( update_op_I ),
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.update_op_II ( update_op_II ),
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.update_op_IV ( update_op_IV )
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);
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wire up_midop_I = { ~cur[4], cur[3:0] } == req_opch_I;
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wire up_midop_II = { ~cur[4], cur[3:0] } == req_opch_II;
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wire up_midop_IV = { ~cur[4], cur[3:0] } == req_opch_IV;
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jt12_csr u_csr1(
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.rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.din ( din ),
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.shift_in ( shift_middle ),
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.shift_out ( shift_out ),
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.up_tl ( up_tl ),
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.up_dt1 ( up_dt1 ),
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.up_ks_ar ( up_ks_ar ),
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.up_amen_dr ( up_amen_dr ),
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.up_sr ( up_sr ),
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.up_sl_rr ( up_sl_rr ),
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.up_ssgeg ( up_ssgeg ),
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// update in the middle:
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.update_op_I ( up_midop_I ),
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.update_op_II ( up_midop_II ),
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.update_op_IV ( up_midop_IV )
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);
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end
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else begin // YM2203 only has one CSR
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jt12_csr u_csr0(
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.rst ( rst ),
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.clk ( clk ),
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.clk_en ( clk_en ),
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.din ( din ),
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.shift_in ( shift_out ),
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.shift_out ( shift_out ),
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.up_tl ( up_tl ),
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.up_dt1 ( up_dt1 ),
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.up_ks_ar ( up_ks_ar ),
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.up_amen_dr ( up_amen_dr ),
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.up_sr ( up_sr ),
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.up_sl_rr ( up_sl_rr ),
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.up_ssgeg ( up_ssgeg ),
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.update_op_I ( update_op_I ),
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.update_op_II ( update_op_II ),
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.update_op_IV ( update_op_IV )
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);
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end // else
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endgenerate
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assign { tl_IV, dt1_I, mul_II, ks_II,
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ar_I, amsen_IV, d1r_I, d2r_I,
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sl_I, rr_I, ssg_en_I, ssg_eg_I } = shift_out;
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// memory for CH registers
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jt12_reg_ch #(.NUM_CH(num_ch)) u_regch(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( clk_en ),
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.din ( ch_din ),
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.up_ch ( ch_sel ),
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.latch_fnum ( latch_fnum ),
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.up_fnumlo ( up_fnumlo ),
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.up_alg ( up_alg ),
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.up_pms ( up_pms ),
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.ch ( next_ch ), // next active channel
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.block ( block_I_raw ),
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.fnum ( fnum_I_raw ),
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.fb ( fb_I ),
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.alg ( alg_I ),
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.rl ( rl ),
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.ams_IV ( ams_IV ),
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.pms ( pms_I )
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);
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`endif
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endmodule
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