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50 lines
1.3 KiB
Verilog
50 lines
1.3 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 29-10-2018
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*/
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module jt12_eg_cnt(
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input rst,
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input clk,
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input clk_en /* synthesis direct_enable */,
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input zero,
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output reg [14:0] eg_cnt
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);
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reg [1:0] eg_cnt_base;
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always @(posedge clk, posedge rst) begin : envelope_counter
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if( rst ) begin
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eg_cnt_base <= 2'd0;
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eg_cnt <=15'd0;
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end
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else begin
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if( zero && clk_en ) begin
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// envelope counter increases every 3 output samples,
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// there is one sample every 24 clock ticks
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if( eg_cnt_base == 2'd2 ) begin
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eg_cnt <= eg_cnt + 1'b1;
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eg_cnt_base <= 2'd0;
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end
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else eg_cnt_base <= eg_cnt_base + 1'b1;
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end
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end
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end
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endmodule // jt12_eg_cnt
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