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47 lines
1.5 KiB
Verilog
47 lines
1.5 KiB
Verilog
/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 21-03-2019
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*/
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module jt12_dout(
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// input rst_n,
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input clk, // CPU clock
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input flag_A,
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input flag_B,
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input busy,
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input [5:0] adpcma_flags,
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input adpcmb_flag,
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input [7:0] psg_dout,
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input [1:0] addr,
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output reg [7:0] dout
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);
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parameter use_ssg=0, use_adpcm=0;
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always @(posedge clk) begin
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casez( addr )
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2'b00: dout <= {busy, 5'd0, flag_B, flag_A }; // YM2203
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2'b01: dout <= (use_ssg ==1) ? psg_dout : {busy, 5'd0, flag_B, flag_A };
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2'b1?: dout <= (use_adpcm==1) ?
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{ adpcmb_flag, 1'b0, adpcma_flags } :
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{ busy, 5'd0, flag_B, flag_A };
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endcase
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end
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endmodule // jt12_dout
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