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61 lines
1.5 KiB
Verilog
61 lines
1.5 KiB
Verilog
module vdac
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(
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input wire mode,
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input wire [4:0] o_r, // input from FPGA
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input wire [4:0] o_g,
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input wire [4:0] o_b,
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output wire [7:0] v_r, // output to VDAC
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output wire [7:0] v_g,
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output wire [7:0] v_b
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);
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vdac_lut vdac_lut_r (.mode(mode), .in(o_r), .out(v_r));
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vdac_lut vdac_lut_g (.mode(mode), .in(o_g), .out(v_g));
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vdac_lut vdac_lut_b (.mode(mode), .in(o_b), .out(v_b));
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endmodule
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module vdac_lut
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(
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input wire mode,
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input wire [4:0] in,
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output wire [7:0] out
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);
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reg [7:0] lut;
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assign out = mode ? {in, 3'b0} : lut;
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always @*
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case (in)
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5'd0: lut = 8'd0;
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5'd1: lut = 8'd10;
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5'd2: lut = 8'd21;
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5'd3: lut = 8'd31;
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5'd4: lut = 8'd42;
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5'd5: lut = 8'd53;
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5'd6: lut = 8'd63;
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5'd7: lut = 8'd74;
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5'd8: lut = 8'd85;
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5'd9: lut = 8'd95;
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5'd10: lut = 8'd106;
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5'd11: lut = 8'd117;
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5'd12: lut = 8'd127;
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5'd13: lut = 8'd138;
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5'd14: lut = 8'd149;
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5'd15: lut = 8'd159;
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5'd16: lut = 8'd170;
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5'd17: lut = 8'd181;
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5'd18: lut = 8'd191;
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5'd19: lut = 8'd202;
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5'd20: lut = 8'd213;
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5'd21: lut = 8'd223;
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5'd22: lut = 8'd234;
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5'd23: lut = 8'd245;
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5'd24: lut = 8'd255;
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default: lut = 8'd255;
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endcase
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endmodule
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