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Fixes in General Sound.

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sorgelig
2018-08-21 14:55:05 +08:00
parent 4348feb625
commit ff3ab93d69
3 changed files with 18 additions and 19 deletions
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11
TSConf.sv
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@ -113,7 +113,7 @@ localparam CONF_STR = {
"O12,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;", "O12,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"-;", "-;",
"O34,Stereo mix,None,25%,50%,100%;", "O34,Stereo mix,None,25%,50%,100%;",
"OST,General Sound,512KB,1MB,2MB,4MB;", "OST,General Sound,512KB,1MB,2MB;",
"-;", "-;",
"O67,CPU Speed,3.5MHz,7MHz,14MHz;", "O67,CPU Speed,3.5MHz,7MHz,14MHz;",
"O8,CPU Cache,On,Off;", "O8,CPU Cache,On,Off;",
@ -288,7 +288,7 @@ tsconf tsconf
assign DDRAM_CLK = clk_mem; assign DDRAM_CLK = clk_mem;
wire [21:0] gs_mem_addr; wire [20:0] gs_mem_addr;
wire [7:0] gs_mem_dout; wire [7:0] gs_mem_dout;
wire [7:0] gs_mem_din; wire [7:0] gs_mem_din;
wire gs_mem_rd; wire gs_mem_rd;
@ -299,10 +299,9 @@ reg [7:0] gs_mem_mask;
always_comb begin always_comb begin
gs_mem_mask = 0; gs_mem_mask = 0;
case(status[29:28]) case(status[29:28])
0: if(gs_mem_addr[21:19]) gs_mem_mask = 8'hFF; 0: if(gs_mem_addr[20:19]) gs_mem_mask = 8'hFF;
1: if(gs_mem_addr[21:20]) gs_mem_mask = 8'hFF; 1: if(gs_mem_addr[20]) gs_mem_mask = 8'hFF;
2: if(gs_mem_addr[21] ) gs_mem_mask = 8'hFF; 2,3: gs_mem_mask = 0;
3: gs_mem_mask = 0;
endcase endcase
end end

24
src/sound/gs.v
View File

@ -79,7 +79,7 @@ module gs #(parameter ROMFILE="gs105b.mif")
input WR_n, input WR_n,
input RD_n, input RD_n,
output [21:0] MEM_ADDR, output [20:0] MEM_ADDR,
output [7:0] MEM_DI, output [7:0] MEM_DI,
input [7:0] MEM_DO, input [7:0] MEM_DO,
output MEM_RD, output MEM_RD,
@ -171,7 +171,7 @@ always @(posedge CLK) begin
end end
end end
reg [6:0] port_00; reg [5:0] port_00;
reg [7:0] port_03; reg [7:0] port_03;
reg signed [6:0] port_06, port_07, port_08, port_09; reg signed [6:0] port_06, port_07, port_08, port_09;
reg signed [7:0] ch_a, ch_b, ch_c, ch_d; reg signed [7:0] ch_a, ch_b, ch_c, ch_d;
@ -184,7 +184,7 @@ always @(posedge CLK) begin
else begin else begin
if (~cpu_iorq_n & ~cpu_wr_n) begin if (~cpu_iorq_n & ~cpu_wr_n) begin
case(cpu_a_bus[3:0]) case(cpu_a_bus[3:0])
0: port_00 <= cpu_do_bus[6:0]; 0: port_00 <= cpu_do_bus[5:0];
3: port_03 <= cpu_do_bus; 3: port_03 <= cpu_do_bus;
6: port_06 <= cpu_do_bus[5:0]; 6: port_06 <= cpu_do_bus[5:0];
7: port_07 <= cpu_do_bus[5:0]; 7: port_07 <= cpu_do_bus[5:0];
@ -205,21 +205,21 @@ always @(posedge CLK) begin
end end
wire [7:0] cpu_di_bus = wire [7:0] cpu_di_bus =
(~cpu_mreq_n && !page_addr[6:1]) ? mem_do : (~cpu_mreq_n && ~cpu_rd_n && !page_addr[5:1]) ? mem_do :
(~cpu_mreq_n) ? MEM_DO : (~cpu_mreq_n && ~cpu_rd_n) ? MEM_DO :
(~cpu_iorq_n && cpu_a_bus[3:0] == 1) ? port_BB : (~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 1) ? port_BB :
(~cpu_iorq_n && cpu_a_bus[3:0] == 2) ? port_B3 : (~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 2) ? port_B3 :
(~cpu_iorq_n && cpu_a_bus[3:0] == 4) ? {bit7, 6'b111111, bit0} : (~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {bit7, 6'b111111, bit0} :
8'hFF; 8'hFF;
wire mem_wr = ~cpu_wr_n & ~cpu_mreq_n & |page_addr; wire mem_wr = ~cpu_wr_n & ~cpu_mreq_n & |page_addr;
wire mem_rd = ~cpu_rd_n & ~cpu_mreq_n; wire mem_rd = ~cpu_rd_n & ~cpu_mreq_n;
wire [6:0] page_addr = cpu_a_bus[15] ? port_00 : cpu_a_bus[14]; wire [5:0] page_addr = cpu_a_bus[15] ? port_00 : cpu_a_bus[14];
assign MEM_ADDR = {page_addr, &cpu_a_bus[15:14], cpu_a_bus[13:0]}; assign MEM_ADDR = {page_addr, &cpu_a_bus[15:14], cpu_a_bus[13:0]};
assign MEM_RD = mem_rd && |page_addr[6:1]; assign MEM_RD = mem_rd && |page_addr[5:1];
assign MEM_WR = mem_wr && |page_addr[6:1]; assign MEM_WR = mem_wr && |page_addr[5:1];
assign MEM_DI = cpu_do_bus; assign MEM_DI = cpu_do_bus;
wire [7:0] mem_do; wire [7:0] mem_do;
@ -227,7 +227,7 @@ dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE(ROMFILE)) mem
( (
.clock(CLK), .clock(CLK),
.address_a(MEM_ADDR[15:0]), .address_a(MEM_ADDR[15:0]),
.wren_a(mem_wr && !page_addr[6:1]), .wren_a(mem_wr && !page_addr[5:1]),
.data_a(cpu_do_bus), .data_a(cpu_do_bus),
.q_a(mem_do) .q_a(mem_do)
); );

2
src/tsconf.v
View File

@ -87,7 +87,7 @@ module tsconf(
output SD_CS_N, output SD_CS_N,
// General Sound // General Sound
output [21:0] GS_ADDR, output [20:0] GS_ADDR,
output [7:0] GS_DI, output [7:0] GS_DI,
input [7:0] GS_DO, input [7:0] GS_DO,
output GS_RD, output GS_RD,