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Merge clocks.

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This commit is contained in:
sorgelig
2018-08-23 04:21:28 +08:00
parent 0f9f64b632
commit dd1681896c
6 changed files with 76 additions and 87 deletions
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20
sys/pll/pll_0002.v
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@ -13,12 +13,6 @@ module pll_0002(
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'outclk3'
output wire outclk_3,
// interface 'locked'
output wire locked
);
@ -27,17 +21,17 @@ module pll_0002(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(4),
.output_clock_frequency0("84.000000 MHz"),
.number_of_clocks(2),
.output_clock_frequency0("112.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("84.000000 MHz"),
.phase_shift1("-4357 ps"),
.output_clock_frequency1("112.000000 MHz"),
.phase_shift1("-4352 ps"),
.duty_cycle1(50),
.output_clock_frequency2("56.000000 MHz"),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("28.000000 MHz"),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
@ -86,7 +80,7 @@ module pll_0002(
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_3, outclk_2, outclk_1, outclk_0}),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),