Update sys.

This commit is contained in:
Sorgelig
2023-12-08 17:08:13 +08:00
parent dcaed90e6d
commit d88b97d957
3 changed files with 69 additions and 21 deletions

View File

@ -124,6 +124,12 @@ module sys_top
inout [6:0] USER_IO inout [6:0] USER_IO
); );
`ifdef MISTER_DUAL_SDRAM
`ifndef MISTER_DISABLE_YC
`define MISTER_DISABLE_YC
`endif
`endif
////////////////////// Secondary SD /////////////////////////////////// ////////////////////// Secondary SD ///////////////////////////////////
wire SD_CS, SD_CLK, SD_MOSI; wire SD_CS, SD_CLK, SD_MOSI;

View File

@ -16,14 +16,16 @@ module vga_out
output reg csync_o output reg csync_o
); );
wire [5:0] red = din[23:18]; wire [7:0] red = din[23:16];
wire [5:0] green = din[15:10]; wire [7:0] green = din[15:8];
wire [5:0] blue = din[7:2]; wire [7:0] blue = din[7:0];
// http://marsee101.blog19.fc2.com/blog-entry-2311.html // http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) // Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B)
reg [7:0] y, pb, pr; reg [7:0] y, pb, pr;
reg [23:0] rgb; reg [23:0] rgb;
@ -36,25 +38,25 @@ always @(posedge clk) begin
reg hsync2, vsync2, csync2; reg hsync2, vsync2, csync2;
reg hsync1, vsync1, csync1; reg hsync1, vsync1, csync1;
y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0}); y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}); pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}); pr_1r <= 19'd32768 + {red, 7'd0};
y_1g <= {green, 9'd0} + {green, 2'd0}; y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0};
pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0}; pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green;
pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}; pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0};
y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}; y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue;
pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}; pb_1b <= {blue, 7'd0};
pr_1b <= {blue, 6'd0} + {blue, 3'd0}; pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue;
y_2 <= y_1r + y_1g + y_1b; y_2 <= y_1r + y_1g + y_1b;
pb_2 <= pb_1r - pb_1g + pb_1b; pb_2 <= pb_1r - pb_1g + pb_1b;
pr_2 <= pr_1r - pr_1g - pr_1b; pr_2 <= pr_1r - pr_1g - pr_1b;
y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8]; y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8];
pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8]; pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8];
pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8]; pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8];
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync; hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync; vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;

View File

@ -173,7 +173,7 @@ sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
wire [11:0] wideres = mul_res[11:0] + hsize; wire [11:0] wideres = mul_res[11:0] + hsize;
always @(posedge CLK_VIDEO) begin always @(posedge CLK_VIDEO) begin
reg [11:0] oheight,wres; reg [11:0] oheight,htarget,wres;
reg [12:0] arxf,aryf; reg [12:0] arxf,aryf;
reg [3:0] cnt; reg [3:0] cnt;
reg narrow; reg narrow;
@ -188,11 +188,18 @@ always @(posedge CLK_VIDEO) begin
else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
cnt <= cnt + 1'd1; cnt <= cnt + 1'd1;
case(cnt) case(cnt)
// example ideal and non-ideal cases:
// [1] 720x400 4:3 VGA 80x25 text-mode (non-square pixels)
// [2] 640x480 4:3 VGA graphics mode (square pixels)
// [3] 512x512 4:3 X68000 graphics mode (non-square pixels)
0: begin 0: begin
div_num <= HDMI_HEIGHT; div_num <= HDMI_HEIGHT;
div_den <= vsize; div_den <= vsize;
div_start <= 1; div_start <= 1;
end end
// [1] 1080 / 400 -> 2
// [2] 1080 / 480 -> 2
// [3] 1080 / 512 -> 2
1: if(!div_res[11:0]) begin 1: if(!div_res[11:0]) begin
// screen resolution is lower than video resolution. // screen resolution is lower than video resolution.
@ -206,6 +213,9 @@ always @(posedge CLK_VIDEO) begin
mul_arg2 <= div_res[11:0]; mul_arg2 <= div_res[11:0];
mul_start <= 1; mul_start <= 1;
end end
// [1] 1080 / 400 * 400 -> 800
// [2] 1080 / 480 * 480 -> 960
// [3] 1080 / 512 * 512 -> 1024
2: begin 2: begin
oheight <= mul_res[11:0]; oheight <= mul_res[11:0];
@ -219,24 +229,39 @@ always @(posedge CLK_VIDEO) begin
mul_arg2 <= arx_i; mul_arg2 <= arx_i;
mul_start <= 1; mul_start <= 1;
end end
// [1] 1080 / 400 * 400 * 4 -> 3200
// [2] 1080 / 480 * 480 * 4 -> 3840
// [3] 1080 / 512 * 512 * 4 -> 4096
4: begin 4: begin
div_num <= mul_res; div_num <= mul_res;
div_den <= ary_i; div_den <= ary_i;
div_start <= 1; div_start <= 1;
end end
// [1] 1080 / 480 * 480 * 4 / 3 -> 1066
// [2] 1080 / 480 * 480 * 4 / 3 -> 1280
// [3] 1080 / 512 * 512 * 4 / 3 -> 1365
// saved as htarget
5: begin 5: begin
htarget <= div_res[11:0];
div_num <= div_res; div_num <= div_res;
div_den <= hsize; div_den <= hsize;
div_start <= 1; div_start <= 1;
end end
// computes wide scaling factor as a ceiling division
// [1] 1080 / 400 * 400 * 4 / 3 / 720 -> 1
// [2] 1080 / 480 * 480 * 4 / 3 / 640 -> 2
// [3] 1080 / 512 * 512 * 4 / 3 / 512 -> 2
6: begin 6: begin
mul_arg1 <= hsize; mul_arg1 <= hsize;
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
mul_start <= 1; mul_start <= 1;
end end
// [1] 1080 / 400 * 400 * 4 / 3 / 720 * 720 -> 720
// [2] 1080 / 480 * 480 * 4 / 3 / 640 * 640 -> 1280
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
7: if(mul_res <= HDMI_WIDTH) begin 7: if(mul_res <= HDMI_WIDTH) begin
cnt <= 10; cnt <= 10;
@ -247,17 +272,32 @@ always @(posedge CLK_VIDEO) begin
div_den <= hsize; div_den <= hsize;
div_start <= 1; div_start <= 1;
end end
// [1] 1920 / 720 -> 2
// [2] 1920 / 640 -> 3
// [3] 1920 / 512 -> 3
9: begin 9: begin
mul_arg1 <= hsize; mul_arg1 <= hsize;
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
mul_start <= 1; mul_start <= 1;
end end
// [1] 1920 / 720 * 720 -> 1440
// [2] 1920 / 640 * 640 -> 1920
// [3] 1920 / 512 * 512 -> 1536
10: begin 10: begin
narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH); narrow <= ((htarget - mul_res[11:0]) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
wres <= wideres; wres <= mul_res[11:0] == htarget ? mul_res[11:0] : wideres;
end end
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
// [3] 1365 - 1024 = 341 <= 1536 - 1365 = 171 || 1536 > 1920 -> false
// 1. narrow flag is true when mul_res[11:0] narrow width is closer to
// htarget aspect ratio target width or when wideres wider width
// does not fit to the screen.
// 2. wres becomes wideres only when mul_res[11:0] narrow width not equal
// to target width, meaning it is not optimal for source aspect ratio.
// otherwise it is set to narrow width that is optimal.
11: begin 11: begin
case(SCALE) case(SCALE)