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https://github.com/UzixLS/TSConf_MiST.git
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Update sys.
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@ -124,6 +124,12 @@ module sys_top
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inout [6:0] USER_IO
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);
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`ifdef MISTER_DUAL_SDRAM
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`ifndef MISTER_DISABLE_YC
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`define MISTER_DISABLE_YC
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`endif
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`endif
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////////////////////// Secondary SD ///////////////////////////////////
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wire SD_CS, SD_CLK, SD_MOSI;
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@ -16,14 +16,16 @@ module vga_out
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output reg csync_o
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);
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wire [5:0] red = din[23:18];
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wire [5:0] green = din[15:10];
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wire [5:0] blue = din[7:2];
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wire [7:0] red = din[23:16];
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wire [7:0] green = din[15:8];
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wire [7:0] blue = din[7:0];
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// http://marsee101.blog19.fc2.com/blog-entry-2311.html
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// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
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// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
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// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
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// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B)
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// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B)
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// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B)
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reg [7:0] y, pb, pr;
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reg [23:0] rgb;
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@ -36,25 +38,25 @@ always @(posedge clk) begin
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reg hsync2, vsync2, csync2;
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reg hsync1, vsync1, csync1;
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y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0});
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pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0});
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pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0});
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y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
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pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
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pr_1r <= 19'd32768 + {red, 7'd0};
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y_1g <= {green, 9'd0} + {green, 2'd0};
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pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0};
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pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0};
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y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0};
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pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green;
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pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0};
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y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0};
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pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0};
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pr_1b <= {blue, 6'd0} + {blue, 3'd0};
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y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue;
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pb_1b <= {blue, 7'd0};
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pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue;
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y_2 <= y_1r + y_1g + y_1b;
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pb_2 <= pb_1r - pb_1g + pb_1b;
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pr_2 <= pr_1r - pr_1g - pr_1b;
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y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
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pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8];
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pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8];
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y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8];
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pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8];
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pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8];
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hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
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vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
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@ -173,7 +173,7 @@ sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
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wire [11:0] wideres = mul_res[11:0] + hsize;
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always @(posedge CLK_VIDEO) begin
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reg [11:0] oheight,wres;
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reg [11:0] oheight,htarget,wres;
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reg [12:0] arxf,aryf;
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reg [3:0] cnt;
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reg narrow;
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@ -188,11 +188,18 @@ always @(posedge CLK_VIDEO) begin
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else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
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cnt <= cnt + 1'd1;
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case(cnt)
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// example ideal and non-ideal cases:
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// [1] 720x400 4:3 VGA 80x25 text-mode (non-square pixels)
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// [2] 640x480 4:3 VGA graphics mode (square pixels)
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// [3] 512x512 4:3 X68000 graphics mode (non-square pixels)
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0: begin
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div_num <= HDMI_HEIGHT;
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div_den <= vsize;
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div_start <= 1;
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end
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// [1] 1080 / 400 -> 2
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// [2] 1080 / 480 -> 2
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// [3] 1080 / 512 -> 2
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1: if(!div_res[11:0]) begin
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// screen resolution is lower than video resolution.
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@ -206,6 +213,9 @@ always @(posedge CLK_VIDEO) begin
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mul_arg2 <= div_res[11:0];
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mul_start <= 1;
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end
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// [1] 1080 / 400 * 400 -> 800
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// [2] 1080 / 480 * 480 -> 960
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// [3] 1080 / 512 * 512 -> 1024
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2: begin
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oheight <= mul_res[11:0];
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@ -219,24 +229,39 @@ always @(posedge CLK_VIDEO) begin
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mul_arg2 <= arx_i;
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mul_start <= 1;
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end
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// [1] 1080 / 400 * 400 * 4 -> 3200
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// [2] 1080 / 480 * 480 * 4 -> 3840
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// [3] 1080 / 512 * 512 * 4 -> 4096
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4: begin
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div_num <= mul_res;
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div_den <= ary_i;
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div_start <= 1;
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end
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// [1] 1080 / 480 * 480 * 4 / 3 -> 1066
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// [2] 1080 / 480 * 480 * 4 / 3 -> 1280
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// [3] 1080 / 512 * 512 * 4 / 3 -> 1365
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// saved as htarget
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5: begin
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htarget <= div_res[11:0];
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div_num <= div_res;
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div_den <= hsize;
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div_start <= 1;
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end
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// computes wide scaling factor as a ceiling division
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// [1] 1080 / 400 * 400 * 4 / 3 / 720 -> 1
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// [2] 1080 / 480 * 480 * 4 / 3 / 640 -> 2
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// [3] 1080 / 512 * 512 * 4 / 3 / 512 -> 2
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6: begin
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mul_arg1 <= hsize;
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mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
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mul_start <= 1;
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end
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// [1] 1080 / 400 * 400 * 4 / 3 / 720 * 720 -> 720
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// [2] 1080 / 480 * 480 * 4 / 3 / 640 * 640 -> 1280
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// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
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7: if(mul_res <= HDMI_WIDTH) begin
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cnt <= 10;
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@ -247,17 +272,32 @@ always @(posedge CLK_VIDEO) begin
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div_den <= hsize;
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div_start <= 1;
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end
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// [1] 1920 / 720 -> 2
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// [2] 1920 / 640 -> 3
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// [3] 1920 / 512 -> 3
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9: begin
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mul_arg1 <= hsize;
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mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
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mul_start <= 1;
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end
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// [1] 1920 / 720 * 720 -> 1440
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// [2] 1920 / 640 * 640 -> 1920
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// [3] 1920 / 512 * 512 -> 1536
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10: begin
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narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
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wres <= wideres;
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narrow <= ((htarget - mul_res[11:0]) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
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wres <= mul_res[11:0] == htarget ? mul_res[11:0] : wideres;
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end
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// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
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// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
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// [3] 1365 - 1024 = 341 <= 1536 - 1365 = 171 || 1536 > 1920 -> false
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// 1. narrow flag is true when mul_res[11:0] narrow width is closer to
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// htarget aspect ratio target width or when wideres wider width
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// does not fit to the screen.
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// 2. wres becomes wideres only when mul_res[11:0] narrow width not equal
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// to target width, meaning it is not optimal for source aspect ratio.
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// otherwise it is set to narrow width that is optimal.
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11: begin
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case(SCALE)
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