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zmem: update to latest version.
This commit is contained in:
sorgelig
443
src/cpu/zmem.v
443
src/cpu/zmem.v
@ -1,307 +1,228 @@
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// PentEvo project (c) NedoPC 2008-2009
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//
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// Z80 memory manager: routes ROM/RAM accesses, makes wait-states for 14MHz or stall condition, etc.
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//
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//
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// clk _/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\_/`\
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zclk /```\___/```\___/```\___/```````\_______/```````\_______/```````````````\_______________/```````````````\_______________/`
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zpos `\___/```\___/```\___/```\___________/```\___________/```\___________________________/```\___________________________/```\
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// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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// zneg _/```\___/```\___/```\_______/```\___________/```\___________________/```\___________________________/```\________________
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module zmem
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(
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input wire clk,
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input wire c0, c1, c2, c3,
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input wire zpos,
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input clk,
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input c0, c1, c2, c3,
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input zneg, // strobes which show positive and negative edges of zclk
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input zpos,
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// Z80
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input wire rst,
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input wire [15:0] za,
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output wire [ 7:0] zd_out, // output to Z80 bus
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output wire zd_ena, // output to Z80 bus enable
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input rst,
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input [15:0] za,
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output [ 7:0] zd_out, // output to Z80 bus
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output zd_ena, // output to Z80 bus enable
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input wire opfetch,
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input wire opfetch_s,
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input wire mreq,
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input wire memrd,
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input wire memwr,
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input wire memwr_s,
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input opfetch,
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input opfetch_s,
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input mreq,
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input memrd,
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input memwr,
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input memwr_s,
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input wire [ 1:0] turbo, // 2'b00 - 3.5,
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// 2'b01 - 7.0,
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// 2'b1x - 14.0
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input wire [3:0] cache_en,
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input wire [3:0] memconf,
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input wire [31:0] xt_page,
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output wire [7:0] xtpage_0,
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input [ 1:0] turbo, // 2'b00 - 3.5,
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// 2'b01 - 7.0,
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// 2'b1x - 14.0
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input [3:0] cache_en,
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input [3:0] memconf,
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input [31:0] xt_page,
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output wire [4:0] rompg,
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output wire csrom,
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output wire romoe_n,
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output wire romwe_n,
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output [4:0] rompg,
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output csrom,
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output romoe_n,
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output romwe_n,
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output wire csvrom,
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output wire dos,
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output wire dos_on,
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output wire dos_off,
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output wire dos_change,
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output wire vdos,
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output reg pre_vdos,
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input wire vdos_on,
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input wire vdos_off,
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output dos,
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output dos_on,
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output dos_off,
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output vdos,
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output reg pre_vdos,
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input vdos_on,
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input vdos_off,
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// DRAM
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output wire cpu_req,
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output wire [20:0] cpu_addr,
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output wire cpu_wrbsel,
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input wire [15:0] cpu_rddata,
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input wire cpu_next,
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input wire cpu_strobe,
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input wire cpu_latch,
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output wire cpu_stall, // for zclock
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input wire loader,
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input wire testkey, // DEBUG!!!
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input wire intt, // DEBUG!!!
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output wire [3:0] tst
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output cpu_req,
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output [20:0] cpu_addr,
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output cpu_wrbsel,
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input [15:0] cpu_rddata,
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input cpu_next,
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input cpu_strobe,
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input cpu_latch,
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output cpu_stall // for zclock
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);
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assign tst[0] = memwr && win0;
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assign tst[1] = rw_en;
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assign tst[2] = ramwr;
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assign tst[3] = 1'b0;
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assign xtpage_0 = xtpage[0];
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//assign xtpage_0 = { 4'b0, vdos, memconf[2], ~dos, memconf[0]};
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//---SELECT ROM PAGE0---------
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//localparam DOS_RESET = 1'h1; //DOS-ON
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localparam DOS_RESET = 1'h0; //DOS-OFF
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// controls
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wire rom128 = memconf[0];
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wire w0_we = memconf[1];
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wire w0_map_n = memconf[2];
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wire w0_ram = memconf[3];
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// pager
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wire [1:0] win = za[15:14];
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wire win0 = ~|win; // PAGE 1,2,3 (not PAGE0)
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// loader = 1 : при выборе Bank3 - ВСЕГДА ПОДКЛЮЧЕНА ВЕРХНЯЯ ПАМЯТЬ - vROM
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// загружаю RОМ через Bank3, запись всегда разрешена
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wire rw_en = !win0 || memconf[1] || vdos; // =1 : WRITE ENABLE for PAGE0 when memconf[1]=1 or vDOS
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//memconf[1] = 1 BANK0 WR_EN, 0 - DIS
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//wire rw_en = !win0 || memconf[3] || memconf[1] || vdos; // WRITE EN for ALL Win if -RAM
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wire [7:0] page = xtpage[win];
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wire [1:0] win = za[15:14];
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wire win0 = ~|win;
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wire ramwr_en = !win0 || w0_we || vdos;
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wire rom_n_ram = win0 && !w0_ram && !vdos;
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wire [7:0] page = xtpage[win];
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assign rompg = xtpage[0][4:0];
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assign csrom = 1'b0; // csvrom && !loader; // 1'b0; //- сигнал ЗАПРЕЩЕНИЯ ЗАПИСИ в ВИРУАЛЬНОЕ ПЗУ
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assign csvrom = win0 && !memconf[3] && !vdos; //- сигнал ДОСТУПА К ВИРУТАЛЬНОМУ ПЗУ
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// memconf[3] = 1-RAM, =0-ROM
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//assign csvrom = win0 && !memconf[3] && !vdos && !(memconf [1] && memwr); // - если WR EN - to RAM ???
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wire [7:0] xtpage[0:3];
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assign xtpage[0] = vdos ? 8'hFF : {xt_page[7:2], memconf[2] ? xt_page[1:0] : {~dos, memconf[0]}};
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assign xtpage[1] = xt_page[15:8];
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assign xtpage[2] = xt_page[23:16];
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assign xtpage[3] = xt_page[31:24]; //rampage[3]
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wire [7:0] xtpage[0:3];
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assign xtpage[0] = vdos ? 8'hFF : {xt_page[7:2], w0_map_n ? xt_page[1:0] : {~dos, rom128}};
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assign xtpage[1] = xt_page[15:8];
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assign xtpage[2] = xt_page[23:16];
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assign xtpage[3] = xt_page[31:24];
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// ROM chip
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assign csrom = rom_n_ram;
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assign romoe_n = !memrd;
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assign romwe_n = !(memwr && w0_we);
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assign rompg = xtpage[0][4:0];
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// RAM
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assign zd_ena = !rom_n_ram && memrd;
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wire ramreq = !rom_n_ram && ((memrd && !cache_hit_en) || (memwr && ramwr_en));
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// DOS signal control
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assign dos_on = win0 && opfetch_s && (za[13:8]==6'h3D) && memconf[0] && !memconf[2];
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//assign dos_on = win0 && opfetch_s && (za[13:8]==6'h3D) && memconf[0];
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assign dos_off = !win0 && opfetch_s && !vdos;
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//assign dos_off = !win0 && opfetch_s;
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assign dos_change = (dos_off && dos_r) || (dos_on && !dos_r);
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assign dos_on = win0 && opfetch_s && (za[13:8]==6'h3D) && rom128 && !w0_map_n;
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assign dos_off = !win0 && opfetch_s && !vdos;
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//assign dos = (dos_on || dos_off) ^^ dos_r; // to make dos appear 1 clock earlier than dos_r
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//assign dos = (dos_on || dos_r);
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assign dos = (dos_on || dos_r) && !dos_off;
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reg dos_r;
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always @(posedge clk)
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if (rst)
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//dos_r <= 1'b0;
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dos_r <= DOS_RESET; //=1 ON
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else if (dos_off)
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dos_r <= 1'b0;
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else if (dos_on)
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dos_r <= 1'b1;
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assign dos = (dos_on || dos_off) ^^ dos_r; // to make dos appear 1 clock earlier than dos_r
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reg dos_r;
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always @(posedge clk) begin
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if (rst) dos_r <= 0;
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else if (dos_off) dos_r <= 0;
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else if (dos_on) dos_r <= 1;
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end
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// VDOS signal control
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// vdos turn on/off is delayed till next opfetch due to INIR that writes right after iord cycle
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assign vdos = opfetch ? pre_vdos : vdos_r; // vdos appears as soon as first opfetch
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// vdos turn on/off is delayed till next opfetch due to INIR that writes right after iord cycle
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assign vdos = opfetch ? pre_vdos : vdos_r; // vdos appears as soon as first opfetch
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reg vdos_r;
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always @(posedge clk)
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if (rst || vdos_off)
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begin
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pre_vdos <= 1'b0;
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vdos_r <= 1'b0;
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reg vdos_r;
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always @(posedge clk) begin
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if (rst || vdos_off) begin
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pre_vdos <= 0;
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vdos_r <= 0;
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end
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else if (vdos_on)
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pre_vdos <= 1'b1;
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else if (opfetch_s)
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vdos_r <= pre_vdos;
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else if (vdos_on) pre_vdos <= 1;
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else if (opfetch_s) vdos_r <= pre_vdos;
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end
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// ===========================================================================
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// address, data in and data out
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assign cpu_wrbsel = za[0];
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assign cpu_addr[20:0] = {page, za[13:1]};
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wire [15:0] mem_d = cpu_latch ? cpu_rddata : cache_d;
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assign zd_out = ~cpu_wrbsel ? mem_d[7:0] : mem_d[15:8];
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// Z80 controls
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assign romoe_n = !memrd;
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assign romwe_n = !(memwr && rw_en);
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assign cpu_req = turbo14 ? cpureq_14 : cpureq_357;
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assign cpu_stall = turbo14 ? stall14 : stall357;
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wire turbo14 = turbo[1];
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wire ramreq = mreq && !csrom;
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wire ramrd = memrd && !csrom;
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wire ramwr = memwr && !csrom && rw_en;
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wire ramwr_s = memwr_s && !csrom && rw_en;
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assign zd_ena = memrd && !csrom;
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assign cpu_req = turbo14 ? cpureq_14 : cpureq_357;
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assign cpu_stall = turbo14 ? stall14 : stall357;
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// 7/3.5MHz support
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wire cpureq_357 = ramreq && !ramreq_r;
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wire stall357 = cpureq_357 && !cpu_next;
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wire turbo14 = turbo[1];
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// 7/3.5MHz support =========================================
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wire cpureq_357 = (ramrd_zs && !cache_hit_en) || ramwr_zs;
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wire stall357 = cpureq_357 && !cpu_next;
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reg ramreq_r;
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always @(posedge clk) if (c3 && !cpu_stall) ramreq_r <= ramreq;
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wire ramwr_zs = ramwr && !ramwr_zr;
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wire ramrd_zs = ramrd && !ramrd_zr;
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// 14MHz support
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// wait tables:
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//
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// M1 opcode fetch, dram_beg concurs with:
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// c3: +3
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// c2: +4
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// c1: +5
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// c0: +6
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//
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// memory read, dram_beg concurs with:
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// c3: +2
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// c2: +3
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// c1: +4
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// c0: +5
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//
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// memory write: no wait
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//
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// special case: if dram_beg pulses 1 when cpu_next is 0,
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// unconditional wait has to be performed until cpu_next is 1, and
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// then wait as if dram_beg would concur with c0
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reg ramrd_zr, ramwr_zr;
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always @(posedge clk)
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if (c3 && !cpu_stall)
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begin
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ramrd_zr <= ramrd;
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ramwr_zr <= ramwr;
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end
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// memrd, opfetch - wait till c3 && cpu_next,
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// memwr - wait till cpu_next
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// 14MHz support ============================================
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// wait tables:
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//
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// M1 opcode fetch, dram_beg concurs with:
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// c3: +3
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// c2: +4
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// c1: +5
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// c0: +6
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//
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// memory read, dram_beg concurs with:
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// c3: +2
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// c2: +3
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// c1: +4
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// c0: +5
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//
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// memory write: no wait
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//
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// special case: if dram_beg pulses 1 when cpu_next is 0,
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// unconditional wait has to be performed until cpu_next is 1, and
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// then wait as if dram_beg would concur with c0
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wire cpureq_14 = dram_beg || pending_cpu_req;
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wire stall14 = stall14_ini || stall14_cyc || stall14_fin;
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// memrd, opfetch - wait till c3 && cpu_next,
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// memwr - wait till cpu_next
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wire cpureq_14 = dram_beg || pending_cpu_req;
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//wire stall14 = stall14_ini || stall14_cyc || stall14_fin; //- not work
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wire stall14 = stall14_ini || stall14_cyc; //WORK
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wire dram_beg = (!cache_hit_en && ( memconf[3] ? 1'b1 : ramrd ) || ramwr) && zpos && ramreq_s_n; //-- N2
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//if BANK0-RAM, WR enable all time for 14 MHz
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wire ramreq_s_n = ramreq_r_n && ramreq;
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reg ramreq_r_n;
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always @(posedge clk) if (zpos) ramreq_r_n <= !mreq;
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wire dram_beg = ramreq && !pre_ramreq_r && zneg;
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reg pending_cpu_req;
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always @(posedge clk)
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if (rst)
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pending_cpu_req <= 1'b0;
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else if (cpu_next && c3)
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pending_cpu_req <= 1'b0;
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else if (dram_beg)
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pending_cpu_req <= 1'b1;
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reg pre_ramreq_r;
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always @(posedge clk) if (zneg) pre_ramreq_r <= ramreq;
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wire stall14_ini = dram_beg && (!cpu_next || opfetch || memrd); // no wait at all in write cycles, if next dram cycle is available
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wire stall14_cyc = memrd ? stall14_cycrd : !cpu_next;
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reg pending_cpu_req;
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always @(posedge clk) begin
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if (rst) pending_cpu_req <= 0;
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else if (cpu_next && c3) pending_cpu_req <= 0;
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else if (dram_beg) pending_cpu_req <= 1;
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end
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wire stall14_ini = dram_beg && (!cpu_next || opfetch || memrd); // no wait at all in write cycles, if next dram cycle is available
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wire stall14_cyc = memrd ? stall14_cycrd : !cpu_next;
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reg stall14_cycrd;
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always @(posedge clk)
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if (rst)
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stall14_cycrd <= 1'b0;
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else if (cpu_next && c3)
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stall14_cycrd <= 1'b0;
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else if (dram_beg && (!c3 || !cpu_next) && (opfetch || memrd))
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stall14_cycrd <= 1'b1;
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reg stall14_cycrd;
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always @(posedge clk) begin
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if (rst) stall14_cycrd <= 0;
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else if (cpu_next && c3) stall14_cycrd <= 0;
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else if (dram_beg && (!c3 || !cpu_next) && (opfetch || memrd)) stall14_cycrd <= 1;
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end
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reg stall14_fin;
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always @(posedge clk)
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if (rst)
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stall14_fin <= 1'b0;
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else if (stall14_fin && ((opfetch && cc[0]) || (memrd && cc[1])))
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stall14_fin <= 1'b0;
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else if (cpu_next && c3 && cpu_req && (opfetch || memrd))
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stall14_fin <= 1'b1;
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reg stall14_fin;
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always @(posedge clk) begin
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if (rst) stall14_fin <= 0;
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else if (stall14_fin && ((opfetch && c1) || (memrd && c2))) stall14_fin <= 0;
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else if (cpu_next && c3 && cpu_req && (opfetch || memrd)) stall14_fin <= 1;
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end
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wire [1:0] cc = turbo[0] ? {c1, c0} : {c2, c1}; // normal or overclock
|
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// cache
|
||||
// wire cache_hit = (ch_addr[7:2] != 6'b011100) && (cpu_hi_addr == cache_a) && cache_v; // debug for BM
|
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wire cache_hit = (cpu_hi_addr == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid
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wire cache_hit_en = cache_hit && cache_en[win];
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wire cache_inv = cache_hit && !rom_n_ram && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address
|
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// address, data in and data out =============================================
|
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assign cpu_wrbsel = za[0];
|
||||
assign cpu_addr[20:0] = {page, za[13:1]};
|
||||
wire [15:0] mem_d = cpu_latch ? cpu_rddata : cache_d;
|
||||
//assign zd_out = ~cpu_wrbsel ? cpu_rddata[7:0] : cpu_rddata[15:8];
|
||||
assign zd_out = ~cpu_wrbsel ? mem_d[7:0] : mem_d[15:8];
|
||||
wire [12:0] cpu_hi_addr = {page[7:0], za[13:9]};
|
||||
wire [12:0] cache_a;
|
||||
wire [7:0] ch_addr = cpu_addr[7:0];
|
||||
|
||||
//=================================================================
|
||||
// CACHE ==INPUT:ramwr,csvrom,cpu_addr,cpu_rddata =================
|
||||
|
||||
wire [7:0] ch_addr1 = cpu_addr[7:0];
|
||||
wire [12:0] cpu_hi_addr1 = cpu_addr[20:8];
|
||||
wire csvrom1 = csvrom;
|
||||
|
||||
reg [7:0] ch_addr2;
|
||||
reg [12:0] cpu_hi_addr2;
|
||||
reg csvrom2;
|
||||
always @(posedge clk) //- !clk
|
||||
if (c0) // ready for cx ------------c1 -not stable
|
||||
begin //------------c0 -0k
|
||||
ch_addr2 <= cpu_addr[7:0]; //--c3 -not stable
|
||||
cpu_hi_addr2 <= cpu_addr[20:8];
|
||||
csvrom2 <= csvrom;
|
||||
end
|
||||
//----------------------------------
|
||||
//===========================================================
|
||||
wire [12:0] cache_a; //address from CACHE
|
||||
wire [15:0] cache_d; //data from CACHE
|
||||
wire cache_v; //data valid
|
||||
wire [1:0] cache_tmp; //empty 16bit: 2 cache_tmp + csvrom + 13cpu_hi_addr1
|
||||
|
||||
dpram #(.DATAWIDTH(16), .ADDRWIDTH(9)) cache_data
|
||||
(
|
||||
.clock (clk), // -- CLK
|
||||
.address_b ({csvrom1, ch_addr1}), // ADDR for RD
|
||||
.address_a (loader ? za[8:0] : cpu_strobe ? {csvrom2, ch_addr2} : {csvrom1, ch_addr1}),//WR
|
||||
//-----------------CACHE DATA -------------------------
|
||||
.wren_a (loader ? 1'b1 : cpu_strobe), //c2 -strobe
|
||||
.data_a (loader ? 16'b0 : cpu_rddata), //<=====
|
||||
.q_b (cache_d) // ==> data from CACHE
|
||||
);
|
||||
wire [15:0] cache_d;
|
||||
wire cache_v;
|
||||
|
||||
dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) cache_data
|
||||
(
|
||||
.clock(clk),
|
||||
.address_a(ch_addr),
|
||||
.data_a(cpu_rddata),
|
||||
.wren_a(cpu_strobe),
|
||||
.address_b(ch_addr),
|
||||
.q_b(cache_d)
|
||||
);
|
||||
|
||||
dpram #(.DATAWIDTH(14), .ADDRWIDTH(8)) cache_addr
|
||||
(
|
||||
.clock(clk),
|
||||
.address_a(ch_addr),
|
||||
.data_a({!cache_inv, cpu_hi_addr}),
|
||||
.wren_a(cpu_strobe || cache_inv),
|
||||
.address_b(ch_addr),
|
||||
.q_b({cache_v, cache_a})
|
||||
);
|
||||
|
||||
dpram #(.DATAWIDTH(16), .ADDRWIDTH(9)) cache_addr
|
||||
(
|
||||
.clock (clk), //---- CLK
|
||||
.address_b ({csvrom1, ch_addr1}), //
|
||||
.address_a (loader ? za[8:0] : cpu_strobe ? {csvrom2, ch_addr2} : {csvrom1, ch_addr1}), //WR
|
||||
//--------------arbiter.cpu_strobe <= curr_cpu && cpu_rnw_r;
|
||||
.q_b ({cache_tmp, cache_v, cache_a}), // valid, addr from CACHE
|
||||
.data_a (loader ? 16'b0 : cpu_strobe ? {cache_tmp, 1'b1, cpu_hi_addr2} : {2'b0, 1'b0, 8'b0}), //wrdata
|
||||
.wren_a (loader ? 1'b1 : (cpu_strobe || cache_inv)) //c2 -strobe
|
||||
);
|
||||
//-----------
|
||||
wire cache_hit = (cpu_hi_addr1 == cache_a) && cache_v;
|
||||
//---ONLY RAM
|
||||
//wire cache_hit = !csvrom1 && (cpu_hi_addr1 == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid
|
||||
//---ONLY ROM
|
||||
//wire cache_hit = csvrom1 && (cpu_hi_addr1 == cache_a) && cache_v;
|
||||
|
||||
//wire cache_hit_en = (cache_hit && cache_en) ;
|
||||
wire cache_hit_en = (cache_hit && (cache_en[win] || csvrom)) ;
|
||||
wire cache_inv = ramwr_s && cache_hit; // cache invalidation should be only performed if write happens to cached address
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user