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Update turbosound.

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sorgelig
2020-05-11 23:43:24 +08:00
parent 5a66d5ec1c
commit c08d8479be
51 changed files with 4523 additions and 3446 deletions
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172
rtl/sound/turbosound.sv
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@ -23,115 +23,157 @@
module turbosound
(
input RESET, // Chip RESET (set all Registers to '0', active high)
input CLK, // Global clock
input CE_CPU, // CPU Clock enable
input CE_YM, // YM2203 Master Clock enable x2 (due to YM2612 model!)
input CE, // YM2203 Master Clock enable
input BDIR, // Bus Direction (0 - read , 1 - write)
input BC, // Bus control
input [7:0] DI, // Data In
output [7:0] DO, // Data Out
output [11:0] CHANNEL_L, // Output channel L
output [11:0] CHANNEL_R, // Output channel R
output ACTIVE
output [11:0] CHANNEL_R // Output channel R
);
reg RESET_s;
reg BDIR_s;
reg BC_s;
reg [7:0] DI_s;
always_ff @(posedge CLK) begin
reg RESET_d;
reg BDIR_d;
reg BC_d;
reg [7:0] DI_d;
RESET_d <= RESET;
BDIR_d <= BDIR;
BC_d <= BC;
DI_d <= DI;
RESET_s <= RESET_d;
BDIR_s <= BDIR_d;
BC_s <= BC_d;
DI_s <= DI_d;
end
// AY1 selected by default
reg ay_select = 1;
reg stat_sel = 1;
reg fm_ena = 0;
reg ym_wr = 0;
reg [7:0] ym_di;
always_ff @(posedge CLK or posedge RESET) begin
if (RESET) begin
always_ff @(posedge CLK or posedge RESET_s) begin
reg old_BDIR = 0;
reg ym_acc = 0;
if (RESET_s) begin
ay_select <= 1;
stat_sel <= 1;
fm_ena <= 0;
ym_acc <= 0;
ym_wr <= 0;
old_BDIR <= 0;
end
else if (BDIR & BC & &DI[7:3]) begin
ay_select <= DI[0];
stat_sel <= DI[1];
fm_ena <= ~DI[2];
else begin
ym_wr <= 0;
old_BDIR <= BDIR_s;
if (~old_BDIR & BDIR_s) begin
if(BC_s & &DI_s[7:3]) begin
ay_select <= DI_s[0];
stat_sel <= DI_s[1];
fm_ena <= ~DI_s[2];
ym_acc <= 0;
end
else if(BC_s) begin
ym_acc <= !DI_s[7:4] || fm_ena;
ym_wr <= !DI_s[7:4] || fm_ena;
end
else begin
ym_wr <= ym_acc;
end
ym_di <= DI_s;
end
end
end
wire [7:0] psg_ch_a_0;
wire [7:0] psg_ch_b_0;
wire [7:0] psg_ch_c_0;
wire [10:0] opn_0;
wire [15:0] opn_0;
wire [7:0] DO_0;
wire WE_0 = ~ay_select & BDIR;
wire ay0_playing;
ym2203 ym2203_0
jt03 ym2203_0
(
.RESET(RESET),
.CLK(CLK),
.CE_CPU(CE_CPU),
.CE_YM(CE_YM),
.rst(RESET_s),
.clk(CLK),
.cen(CE),
.din(ym_di),
.addr((BDIR_s|ym_wr) ? ~BC_s : stat_sel),
.cs_n(ay_select),
.wr_n(~ym_wr),
.dout(DO_0),
.A0(WE_0 ? ~BC : stat_sel),
.WE(WE_0),
.DI(DI),
.DO(DO_0),
.psg_A(psg_ch_a_0),
.psg_B(psg_ch_b_0),
.psg_C(psg_ch_c_0),
.CHANNEL_A(psg_ch_a_0),
.CHANNEL_B(psg_ch_b_0),
.CHANNEL_C(psg_ch_c_0),
.CHANNEL_FM(opn_0),
.PSG_ACTIVE(ay0_playing),
.FM_ENA(fm_ena)
.fm_snd(opn_0)
);
wire [7:0] psg_ch_a_1;
wire [7:0] psg_ch_b_1;
wire [7:0] psg_ch_c_1;
wire [10:0] opn_1;
wire [15:0] opn_1;
wire [7:0] DO_1;
wire WE_1 = ay_select & BDIR;
wire ay1_playing;
ym2203 ym2203_1
jt03 ym2203_1
(
.RESET(RESET),
.CLK(CLK),
.CE_CPU(CE_CPU),
.CE_YM(CE_YM),
.rst(RESET_s),
.clk(CLK),
.cen(CE),
.din(ym_di),
.addr((BDIR_s|ym_wr) ? ~BC_s : stat_sel),
.cs_n(~ay_select),
.wr_n(~ym_wr),
.dout(DO_1),
.A0(WE_1 ? ~BC : stat_sel),
.WE(WE_1),
.DI(DI),
.DO(DO_1),
.psg_A(psg_ch_a_1),
.psg_B(psg_ch_b_1),
.psg_C(psg_ch_c_1),
.CHANNEL_A(psg_ch_a_1),
.CHANNEL_B(psg_ch_b_1),
.CHANNEL_C(psg_ch_c_1),
.CHANNEL_FM(opn_1),
.PSG_ACTIVE(ay1_playing),
.FM_ENA(fm_ena)
.fm_snd(opn_1)
);
assign DO = ay_select ? DO_1 : DO_0;
assign ACTIVE = ay0_playing | ay1_playing | fm_ena;
// Mix channel signals from both AY/YM chips (extending to 9 bits width to prevent clipping)
wire [8:0] sum_ch_a = { 1'b0, psg_ch_a_1 } + { 1'b0, psg_ch_a_0 };
wire [8:0] sum_ch_b = { 1'b0, psg_ch_b_1 } + { 1'b0, psg_ch_b_0 };
wire [8:0] sum_ch_c = { 1'b0, psg_ch_c_1 } + { 1'b0, psg_ch_c_0 };
reg [8:0] sum_ch_a,sum_ch_b,sum_ch_c;
reg [7:0] psg_a,psg_b,psg_c;
reg [11:0] psg_l,psg_r,opn_s;
reg [11:0] ch_l, ch_r;
// Control output channels (Only AY_1 plays if not in TurboSound mode)
wire [7:0] psg_a = ~ay0_playing ? psg_ch_a_1 : sum_ch_a[8:1];
wire [7:0] psg_b = ~ay0_playing ? psg_ch_b_1 : sum_ch_b[8:1];
wire [7:0] psg_c = ~ay0_playing ? psg_ch_c_1 : sum_ch_c[8:1];
always @(posedge CLK) begin
wire signed [11:0] psg_l = {3'b000, psg_a, 1'd0} + {4'b0000, psg_b};
wire signed [11:0] psg_r = {3'b000, psg_c, 1'd0} + {4'b0000, psg_b};
wire signed [11:0] opn_s = {{2{opn_0[10]}}, opn_0[10:1]} + {{2{opn_1[10]}}, opn_1[10:1]};
sum_ch_a <= { 1'b0, psg_ch_a_1 } + { 1'b0, psg_ch_a_0 };
sum_ch_b <= { 1'b0, psg_ch_b_1 } + { 1'b0, psg_ch_b_0 };
sum_ch_c <= { 1'b0, psg_ch_c_1 } + { 1'b0, psg_ch_c_0 };
assign CHANNEL_L = fm_ena ? opn_s + psg_l : psg_l;
assign CHANNEL_R = fm_ena ? opn_s + psg_r : psg_r;
psg_a <= sum_ch_a[8] ? 8'hFF : sum_ch_a[7:0];
psg_b <= sum_ch_b[8] ? 8'hFF : sum_ch_b[7:0];
psg_c <= sum_ch_c[8] ? 8'hFF : sum_ch_c[7:0];
psg_l <= {3'b000, psg_a, 1'd0} + {4'b0000, psg_b};
psg_r <= {3'b000, psg_c, 1'd0} + {4'b0000, psg_b};
opn_s <= {{2{opn_0[15]}}, opn_0[15:6]} + {{2{opn_1[15]}}, opn_1[15:6]};
ch_l <= fm_ena ? $signed(opn_s) + $signed(psg_l) : $signed(psg_l);
ch_r <= fm_ena ? $signed(opn_s) + $signed(psg_r) : $signed(psg_r);
end
assign CHANNEL_L = ch_l;
assign CHANNEL_R = ch_r;
endmodule