uzix/TSConf_MiST
1
0
Fork 0
mirror of https://github.com/UzixLS/TSConf_MiST.git synced 2025-07-19 07:11:22 +03:00
Code Issues Packages Projects Releases Wiki Activity

Update turbosound.

Browse Source
This commit is contained in:
sorgelig
2020-05-11 23:43:24 +08:00
parent 5a66d5ec1c
commit c08d8479be
51 changed files with 4523 additions and 3446 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
rtl/sound/jt12/jt12_sh24.v
View File

@ -22,35 +22,36 @@
module jt12_sh24 #(parameter width=5 )
(
input clk,
input [width-1:0] din,
output reg [width-1:0] st1,
output reg [width-1:0] st2,
output reg [width-1:0] st3,
output reg [width-1:0] st4,
output reg [width-1:0] st5,
output reg [width-1:0] st6,
output reg [width-1:0] st7,
output reg [width-1:0] st8,
output reg [width-1:0] st9,
output reg [width-1:0] st10,
output reg [width-1:0] st11,
output reg [width-1:0] st12,
output reg [width-1:0] st13,
output reg [width-1:0] st14,
output reg [width-1:0] st15,
output reg [width-1:0] st16,
output reg [width-1:0] st17,
output reg [width-1:0] st18,
output reg [width-1:0] st19,
output reg [width-1:0] st20,
output reg [width-1:0] st21,
output reg [width-1:0] st22,
output reg [width-1:0] st23,
output reg [width-1:0] st24
input clk,
input clk_en,
input [width-1:0] din,
output reg [width-1:0] st1,
output reg [width-1:0] st2,
output reg [width-1:0] st3,
output reg [width-1:0] st4,
output reg [width-1:0] st5,
output reg [width-1:0] st6,
output reg [width-1:0] st7,
output reg [width-1:0] st8,
output reg [width-1:0] st9,
output reg [width-1:0] st10,
output reg [width-1:0] st11,
output reg [width-1:0] st12,
output reg [width-1:0] st13,
output reg [width-1:0] st14,
output reg [width-1:0] st15,
output reg [width-1:0] st16,
output reg [width-1:0] st17,
output reg [width-1:0] st18,
output reg [width-1:0] st19,
output reg [width-1:0] st20,
output reg [width-1:0] st21,
output reg [width-1:0] st22,
output reg [width-1:0] st23,
output reg [width-1:0] st24
);
always @(posedge clk) begin
always @(posedge clk) if(clk_en) begin
st24<= st23;
st23<= st22;
st22<= st21;