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Update turbosound.
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sorgelig
@ -1,114 +1,126 @@
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`timescale 1ns / 1ps
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/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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*/
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module jt12_reg(
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input rst,
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input clk,
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input [7:0] din,
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input [2:0] ch,
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input [1:0] op,
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input csm,
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input flag_A,
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input overflow_A,
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input rst,
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input clk,
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input clk_en,
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input [7:0] din,
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input [2:0] ch,
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input [1:0] op,
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input csm,
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input flag_A,
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input overflow_A,
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input up_keyon,
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input up_alg,
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input up_block,
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input up_fnumlo,
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input up_pms,
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input up_dt1,
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input up_tl,
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input up_ks_ar,
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input up_amen_d1r,
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input up_d2r,
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input up_d1l,
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input up_ssgeg,
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input up_keyon,
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input up_alg,
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input up_fnumlo,
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input up_pms,
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input up_dt1,
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input up_tl,
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input up_ks_ar,
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input up_amen_dr,
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input up_sr,
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input up_sl_rr,
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input up_ssgeg,
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output busy,
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output reg ch6op, // 1 when the operator belongs to CH6
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// CH3 Effect-mode operation
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input effect,
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input [10:0] fnum_ch3op2,
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input [10:0] fnum_ch3op3,
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input [10:0] fnum_ch3op1,
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input [ 2:0] block_ch3op2,
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input [ 2:0] block_ch3op3,
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input [ 2:0] block_ch3op1,
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// Pipeline order
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output reg zero,
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output s1_enters,
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output s2_enters,
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output s3_enters,
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output s4_enters,
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// Operator
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output use_prevprev1,
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output use_internal_x,
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output use_internal_y,
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output use_prev2,
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output use_prev1,
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// PG
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output [10:0] fnum_I,
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output [ 2:0] block_I,
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// channel configuration
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output [1:0] rl,
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output reg [2:0] fb_II,
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output [2:0] alg,
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// Operator multiplying
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output [ 3:0] mul_V,
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// Operator detuning
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output [ 2:0] dt1_II,
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// EG
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output [4:0] ar_II, // attack rate
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output [4:0] d1r_II, // decay rate
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output [4:0] d2r_II, // sustain rate
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output [3:0] rr_II, // release rate
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output [3:0] d1l, // sustain level
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output [1:0] ks_III, // key scale
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output ssg_en_II,
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output [2:0] ssg_eg_II,
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output [6:0] tl_VII,
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output [2:0] pms,
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output [1:0] ams_VII,
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output amsen_VII,
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output reg ch6op, // 1 when the operator belongs to CH6
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// CH3 Effect-mode operation
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input effect,
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input [10:0] fnum_ch3op2,
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input [10:0] fnum_ch3op3,
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input [10:0] fnum_ch3op1,
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input [ 2:0] block_ch3op2,
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input [ 2:0] block_ch3op3,
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input [ 2:0] block_ch3op1,
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input [ 5:0] latch_fnum,
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// Pipeline order
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output reg zero,
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output s1_enters,
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output s2_enters,
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output s3_enters,
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output s4_enters,
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// Operator
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output xuse_prevprev1,
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output xuse_internal,
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output yuse_internal,
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output xuse_prev2,
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output yuse_prev1,
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output yuse_prev2,
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// PG
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output [10:0] fnum_I,
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output [ 2:0] block_I,
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// channel configuration
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output [1:0] rl,
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output reg [2:0] fb_II,
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output [2:0] alg_I,
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// Operator multiplying
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output [ 3:0] mul_II,
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// Operator detuning
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output [ 2:0] dt1_I,
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// EG
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output [4:0] ar_I, // attack rate
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output [4:0] d1r_I, // decay rate
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output [4:0] d2r_I, // sustain rate
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output [3:0] rr_I, // release rate
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output [3:0] sl_I, // sustain level
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output [1:0] ks_II, // key scale
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output ssg_en_I,
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output [2:0] ssg_eg_I,
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output [6:0] tl_IV,
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output [2:0] pms_I,
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output [1:0] ams_IV,
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output amsen_IV,
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// envelope operation
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output keyon_II
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// envelope operation
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output keyon_I
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);
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parameter num_ch=6; // Use only 3 (YM2203/YM2610) or 6 (YM2612/YM2608)
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reg [4:0] cnt;
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reg [1:0] next_op, cur_op;
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reg [2:0] next_ch, cur_ch;
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reg last;
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`ifdef SIMULATION
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// These signals need to operate during rst
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// initial state is not relevant (or critical) in real life
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// but we need a clear value during simulation
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// This does not work with NCVERILOG
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initial begin
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cur_op = 2'd0;
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cur_ch = 3'd0;
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last = 1'b0;
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zero = 1'b1;
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end
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`endif
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assign s1_enters = cur_op == 2'b00;
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assign s3_enters = cur_op == 2'b01;
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@ -120,244 +132,239 @@ wire [4:0] cur = { cur_op, cur_ch };
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wire [2:0] fb_I;
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always @(posedge clk) begin
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fb_II <= fb_I;
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ch6op <= next_ch==3'd6;
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end
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always @(posedge clk) if( clk_en ) begin
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fb_II <= fb_I;
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ch6op <= next_ch==3'd6;
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end
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// FNUM and BLOCK
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wire [10:0] fnum_I_raw;
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wire [ 2:0] block_I_raw;
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wire [10:0] fnum_I_raw;
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wire [ 2:0] block_I_raw;
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wire effect_on = effect && (cur_ch==3'd2);
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wire effect_on_s1 = effect_on && (cur_op == 2'd0 );
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wire effect_on_s3 = effect_on && (cur_op == 2'd1 );
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wire effect_on_s2 = effect_on && (cur_op == 2'd2 );
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wire noeffect = ~|{effect_on_s1, effect_on_s3, effect_on_s2};
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wire noeffect = ~|{effect_on_s1, effect_on_s3, effect_on_s2};
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assign fnum_I = ( {11{effect_on_s1}} & fnum_ch3op1 ) |
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( {11{effect_on_s2}} & fnum_ch3op2 ) |
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( {11{effect_on_s3}} & fnum_ch3op3 ) |
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( {11{noeffect}} & fnum_I_raw );
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( {11{effect_on_s2}} & fnum_ch3op2 ) |
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( {11{effect_on_s3}} & fnum_ch3op3 ) |
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( {11{noeffect}} & fnum_I_raw );
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assign block_I =( {3{effect_on_s1}} & block_ch3op1 ) |
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( {3{effect_on_s2}} & block_ch3op2 ) |
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( {3{effect_on_s3}} & block_ch3op3 ) |
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( {3{noeffect}} & block_I_raw );
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( {3{effect_on_s2}} & block_ch3op2 ) |
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( {3{effect_on_s3}} & block_ch3op3 ) |
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( {3{noeffect}} & block_I_raw );
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wire [2:0] ch_II, ch_III, ch_IV, ch_V, ch_VI;
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wire [4:0] req_opch_I = { op, ch };
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wire [4:0] req_opch_II, req_opch_III,
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req_opch_IV, req_opch_V, req_opch_VI;
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jt12_sumch u_opch_II ( .chin(req_opch_I ), .chout(req_opch_II) );
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jt12_sumch u_opch_III( .chin(req_opch_II ), .chout(req_opch_III) );
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jt12_sumch u_opch_IV ( .chin(req_opch_III), .chout(req_opch_IV) );
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jt12_sumch u_opch_V ( .chin(req_opch_IV ), .chout(req_opch_V) );
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jt12_sumch u_opch_VI ( .chin(req_opch_V ), .chout(req_opch_VI) );
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wire [4:0] req_opch_II, req_opch_III,
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req_opch_IV, req_opch_V, req_opch_VI;
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jt12_sumch #(.num_ch(num_ch)) u_opch_II ( .chin(req_opch_I ), .chout(req_opch_II ) );
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jt12_sumch #(.num_ch(num_ch)) u_opch_III( .chin(req_opch_II ), .chout(req_opch_III) );
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jt12_sumch #(.num_ch(num_ch)) u_opch_IV ( .chin(req_opch_III), .chout(req_opch_IV ) );
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jt12_sumch #(.num_ch(num_ch)) u_opch_V ( .chin(req_opch_IV ), .chout(req_opch_V ) );
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// jt12_sumch #(.num_ch(num_ch)) u_opch_VI ( .chin(req_opch_V ), .chout(req_opch_VI) );
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wire update_op_I = cur == req_opch_I;
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wire update_op_II = cur == req_opch_II;
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wire update_op_III= cur == req_opch_III;
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// wire update_op_IV = cur == opch_IV;
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wire update_op_V = cur == req_opch_V;
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// wire update_op_III= cur == req_opch_III;
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wire update_op_IV = cur == req_opch_IV;
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// wire update_op_V = cur == req_opch_V;
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// wire update_op_VI = cur == opch_VI;
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wire [2:0] op_plus1 = op+2'd1;
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wire update_op_VII= cur == { op_plus1[1:0], ch };
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// wire [2:0] op_plus1 = op+2'd1;
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// wire update_op_VII= cur == { op_plus1[1:0], ch };
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// key on/off
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wire [3:0] keyon_op = din[7:4];
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wire [2:0] keyon_ch = din[2:0];
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wire [3:0] keyon_op = din[7:4];
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wire [2:0] keyon_ch = din[2:0];
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// channel data
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wire [1:0] rl_in = din[7:6];
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wire [2:0] fb_in = din[5:3];
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wire [2:0] alg_in = din[2:0];
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wire [2:0] pms_in = din[2:0];
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wire [1:0] ams_in = din[5:4];
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wire [2:0] block_in= din[5:3];
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wire [2:0] fnhi_in = din[2:0];
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wire [7:0] fnlo_in = din;
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// operator data
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wire [2:0] dt1_in = din[6:4];
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wire [3:0] mul_in = din[3:0];
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wire [6:0] tl_in = din[6:0];
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wire [1:0] ks_in = din[7:6];
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wire [4:0] ar_in = din[4:0];
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wire amen_in = din[7];
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wire [4:0] d1r_in = din[4:0];
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wire [4:0] d2r_in = din[4:0];
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wire [3:0] d1l_in = din[7:4];
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wire [3:0] rr_in = din[3:0];
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wire [3:0] ssg_in = din[3:0];
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//wire [1:0] rl_in = din[7:6];
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wire [2:0] fb_in = din[5:3];
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wire [2:0] alg_in = din[2:0];
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wire [2:0] pms_in = din[2:0];
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wire [1:0] ams_in = din[5:4];
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wire [7:0] fnlo_in = din;
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wire [3:0] ssg;
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reg last;
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wire update_ch_I = cur_ch == ch;
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wire update_ch_IV = num_ch==6 ?
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{ ~cur_ch[2], cur_ch[1:0]} == ch : // 6 channels
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cur[1:0] == ch[1:0]; // 3 channels
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wire update_ch_I = cur_ch == ch;
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wire up_alg_ch = up_alg & update_ch_I;
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wire up_block_ch= up_block & update_ch_I;
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wire up_alg_ch = up_alg & update_ch_I;
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wire up_fnumlo_ch=up_fnumlo & update_ch_I;
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wire up_pms_ch = up_pms & update_ch_I;
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// DT1 & MUL
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wire up_dt1_op = up_dt1 & update_op_II;
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wire up_mul_op = up_dt1 & update_op_V;
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// TL
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wire up_tl_op = up_tl & update_op_VII;
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// KS & AR
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wire up_ks_op = up_ks_ar & update_op_III;
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wire up_ar_op = up_ks_ar & update_op_II;
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// AM ON, D1R
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wire up_amen_op = up_amen_d1r & update_op_VII;
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wire up_d1r_op = up_amen_d1r & update_op_II;
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// Sustain Rate (D2R)
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wire up_d2r_op = up_d2r & update_op_II;
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// D1L & RR
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wire up_d1l_op = up_d1l & update_op_I;
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wire up_rr_op = up_d1l & update_op_II;
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// SSG
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//wire up_ssgen_op = up_ssgeg & update_op_I;
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wire up_ssg_op = up_ssgeg & update_op_II;
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wire up = up_alg | up_block | up_fnumlo | up_pms |
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up_dt1 | up_tl | up_ks_ar | up_amen_d1r |
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up_d2r | up_d1l | up_ssgeg | up_keyon;
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wire up_pms_ch = up_pms & update_ch_I;
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wire up_ams_ch = up_pms & update_ch_IV;
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always @(*) begin
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// next <= cur==5'd23 ? 5'd0 : cur +1'b1;
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next_op <= cur_ch==3'd6 ? cur_op+1'b1 : cur_op;
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next_ch <= cur_ch[1:0]==2'b10 ? cur_ch+2'd2 : cur_ch+1'd1;
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// next = cur==5'd23 ? 5'd0 : cur +1'b1;
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if( num_ch==6 ) begin
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next_op = cur_ch==3'd6 ? cur_op+1'b1 : cur_op;
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next_ch = cur_ch[1:0]==2'b10 ? cur_ch+2'd2 : cur_ch+1'd1;
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end else begin // 3 channels
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next_op = cur_ch==3'd2 ? cur_op+1'b1 : cur_op;
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||||
next_ch = cur_ch[1:0]==2'b10 ? 3'd0 : cur_ch+1'd1;
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||||
end
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||||
end
|
||||
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reg busy_op;
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reg up_keyon_long;
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assign busy = busy_op;
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|
||||
|
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always @(posedge clk) begin : up_counter
|
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if( rst ) begin
|
||||
cnt <= 5'h0;
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last <= 1'b0;
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zero <= 1'b1;
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busy_op <= 1'b0;
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up_keyon_long <= 1'b0;
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cur_op <= 2'd0;
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cur_ch <= 3'd0;
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end
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else begin
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||||
{ cur_op, cur_ch } <= { next_op, next_ch };
|
||||
zero <= next == 5'd0;
|
||||
last <= up;
|
||||
if( up && !last ) begin
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||||
cnt <= cur;
|
||||
busy_op <= 1'b1;
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||||
up_keyon_long <= up_keyon;
|
||||
end
|
||||
else if( cnt == cur ) begin
|
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busy_op <= 1'b0;
|
||||
up_keyon_long <= 1'b0;
|
||||
end
|
||||
end
|
||||
if( clk_en ) begin
|
||||
{ cur_op, cur_ch } <= { next_op, next_ch };
|
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zero <= next == 5'd0;
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||||
end
|
||||
end
|
||||
|
||||
jt12_kon u_kon(
|
||||
.rst ( rst ),
|
||||
.clk ( clk ),
|
||||
.keyon_op ( keyon_op ),
|
||||
.keyon_ch ( keyon_ch ),
|
||||
.cur_op ( cur_op ),
|
||||
.cur_ch ( cur_ch ),
|
||||
.up_keyon ( up_keyon_long ),
|
||||
.csm ( csm ),
|
||||
.flag_A ( flag_A ),
|
||||
.overflow_A ( overflow_A),
|
||||
|
||||
.keyon_II ( keyon_II )
|
||||
jt12_kon #(.num_ch(num_ch)) u_kon(
|
||||
.rst ( rst ),
|
||||
.clk ( clk ),
|
||||
.clk_en ( clk_en ),
|
||||
.keyon_op ( keyon_op ),
|
||||
.keyon_ch ( keyon_ch ),
|
||||
.next_op ( next_op ),
|
||||
.next_ch ( next_ch ),
|
||||
.up_keyon ( up_keyon ),
|
||||
.csm ( csm ),
|
||||
// .flag_A ( flag_A ),
|
||||
.overflow_A ( overflow_A),
|
||||
|
||||
.keyon_I ( keyon_I )
|
||||
);
|
||||
|
||||
jt12_mod u_mod(
|
||||
.alg_I ( alg ),
|
||||
.s1_enters ( s1_enters ),
|
||||
.s3_enters ( s3_enters ),
|
||||
.s2_enters ( s2_enters ),
|
||||
.s4_enters ( s4_enters ),
|
||||
|
||||
.use_prevprev1 ( use_prevprev1 ),
|
||||
.use_internal_x( use_internal_x ),
|
||||
.use_internal_y( use_internal_y ),
|
||||
.use_prev2 ( use_prev2 ),
|
||||
.use_prev1 ( use_prev1 )
|
||||
jt12_mod #(.num_ch(num_ch)) u_mod(
|
||||
.alg_I ( alg_I ),
|
||||
.s1_enters ( s1_enters ),
|
||||
.s3_enters ( s3_enters ),
|
||||
.s2_enters ( s2_enters ),
|
||||
.s4_enters ( s4_enters ),
|
||||
|
||||
.xuse_prevprev1 ( xuse_prevprev1 ),
|
||||
.xuse_internal ( xuse_internal ),
|
||||
.yuse_internal ( yuse_internal ),
|
||||
.xuse_prev2 ( xuse_prev2 ),
|
||||
.yuse_prev1 ( yuse_prev1 ),
|
||||
.yuse_prev2 ( yuse_prev2 )
|
||||
);
|
||||
|
||||
// memory for OP registers
|
||||
parameter regop_width=44;
|
||||
wire [43:0] shift_out;
|
||||
|
||||
wire [regop_width-1:0] regop_in, regop_out;
|
||||
generate
|
||||
if( num_ch==6 ) begin
|
||||
// YM2612 / YM3438: Two CSR.
|
||||
wire [43:0] shift_middle;
|
||||
|
||||
jt12_opram u_opram(
|
||||
.clk ( clk ),
|
||||
.wr_addr ( cur ),
|
||||
.rd_addr ( next ),
|
||||
.data ( regop_in ),
|
||||
.q ( regop_out )
|
||||
);
|
||||
jt12_csr u_csr0(
|
||||
.rst ( rst ),
|
||||
.clk ( clk ),
|
||||
.clk_en ( clk_en ),
|
||||
.din ( din ),
|
||||
.shift_in ( shift_out ),
|
||||
.shift_out ( shift_middle ),
|
||||
.up_tl ( up_tl ),
|
||||
.up_dt1 ( up_dt1 ),
|
||||
.up_ks_ar ( up_ks_ar ),
|
||||
.up_amen_dr ( up_amen_dr ),
|
||||
.up_sr ( up_sr ),
|
||||
.up_sl_rr ( up_sl_rr ),
|
||||
.up_ssgeg ( up_ssgeg ),
|
||||
.update_op_I ( update_op_I ),
|
||||
.update_op_II ( update_op_II ),
|
||||
.update_op_IV ( update_op_IV )
|
||||
);
|
||||
|
||||
assign regop_in = {
|
||||
up_tl_op ? tl_in : tl_VII, // 7
|
||||
up_dt1_op ? dt1_in : dt1_II, // 3
|
||||
up_mul_op ? mul_in : mul_V, // 4 - 7
|
||||
up_ks_op ? ks_in : ks_III, // 2 - 16
|
||||
up_ar_op ? ar_in : ar_II, // 5 - 21
|
||||
up_amen_op ? amen_in: amsen_VII,// 1 - 22
|
||||
up_d1r_op ? d1r_in : d1r_II, // 5 - 25
|
||||
up_d2r_op ? d2r_in : d2r_II, // 5 - 30
|
||||
up_d1l_op ? d1l_in : d1l, // 4 - 34
|
||||
up_rr_op ? rr_in : rr_II, // 4 - 38
|
||||
up_ssg_op ? ssg_in[3] : ssg_en_II, // 1 - 39
|
||||
up_ssg_op ? ssg_in[2:0] : ssg_eg_II // 3 - 42
|
||||
};
|
||||
wire up_midop_I = { ~cur[4], cur[3:0] } == req_opch_I;
|
||||
wire up_midop_II = { ~cur[4], cur[3:0] } == req_opch_II;
|
||||
wire up_midop_IV = { ~cur[4], cur[3:0] } == req_opch_IV;
|
||||
|
||||
assign { tl_VII, dt1_II, mul_V, ks_III,
|
||||
ar_II, amsen_VII, d1r_II, d2r_II, d1l, rr_II,
|
||||
ssg_en_II, ssg_eg_II } = regop_out;
|
||||
jt12_csr u_csr1(
|
||||
.rst ( rst ),
|
||||
.clk ( clk ),
|
||||
.clk_en ( clk_en ),
|
||||
.din ( din ),
|
||||
.shift_in ( shift_middle ),
|
||||
.shift_out ( shift_out ),
|
||||
.up_tl ( up_tl ),
|
||||
.up_dt1 ( up_dt1 ),
|
||||
.up_ks_ar ( up_ks_ar ),
|
||||
.up_amen_dr ( up_amen_dr ),
|
||||
.up_sr ( up_sr ),
|
||||
.up_sl_rr ( up_sl_rr ),
|
||||
.up_ssgeg ( up_ssgeg ),
|
||||
// update in the middle:
|
||||
.update_op_I ( up_midop_I ),
|
||||
.update_op_II ( up_midop_II ),
|
||||
.update_op_IV ( up_midop_IV )
|
||||
);
|
||||
end
|
||||
else begin // YM2203 only has one CSR
|
||||
jt12_csr u_csr0(
|
||||
.rst ( rst ),
|
||||
.clk ( clk ),
|
||||
.clk_en ( clk_en ),
|
||||
.din ( din ),
|
||||
.shift_in ( shift_out ),
|
||||
.shift_out ( shift_out ),
|
||||
.up_tl ( up_tl ),
|
||||
.up_dt1 ( up_dt1 ),
|
||||
.up_ks_ar ( up_ks_ar ),
|
||||
.up_amen_dr ( up_amen_dr ),
|
||||
.up_sr ( up_sr ),
|
||||
.up_sl_rr ( up_sl_rr ),
|
||||
.up_ssgeg ( up_ssgeg ),
|
||||
.update_op_I ( update_op_I ),
|
||||
.update_op_II ( update_op_II ),
|
||||
.update_op_IV ( update_op_IV )
|
||||
);
|
||||
end // else
|
||||
endgenerate
|
||||
|
||||
assign { tl_IV, dt1_I, mul_II, ks_II,
|
||||
ar_I, amsen_IV, d1r_I, d2r_I,
|
||||
sl_I, rr_I, ssg_en_I, ssg_eg_I } = shift_out;
|
||||
|
||||
wire [2:0] block_latch, fnum_latch;
|
||||
|
||||
// memory for CH registers
|
||||
// Block/fnum data is latched until fnum low byte is written to
|
||||
// Trying to synthesize this memory as M-9K RAM in Altera devices
|
||||
// turns out worse in terms of resource utilization. Probably because
|
||||
// this memory is already very small. It is better to leave it as it is.
|
||||
parameter regch_width=31;
|
||||
localparam regch_width=25;
|
||||
wire [regch_width-1:0] regch_out;
|
||||
wire [regch_width-1:0] regch_in = {
|
||||
up_block_ch ? { block_in, fnhi_in } : { block_latch, fnum_latch }, // 3+3
|
||||
up_fnumlo_ch? { block_latch, fnum_latch, fnlo_in } : { block_I_raw, fnum_I_raw }, // 14
|
||||
up_alg_ch ? { fb_in, alg_in } : { fb_I, alg },//3+3
|
||||
up_pms_ch ? { ams_in, pms_in } : { ams_VII, pms }//2+2+3
|
||||
up_fnumlo_ch? { latch_fnum, fnlo_in } : { block_I_raw, fnum_I_raw }, // 14
|
||||
up_alg_ch ? { fb_in, alg_in } : { fb_I, alg_I },//3+3
|
||||
up_ams_ch ? ams_in : ams_IV, //2
|
||||
up_pms_ch ? pms_in : pms_I //3
|
||||
};
|
||||
|
||||
assign { block_latch, fnum_latch,
|
||||
block_I_raw, fnum_I_raw,
|
||||
fb_I, alg, ams_VII, pms } = regch_out;
|
||||
assign { block_I_raw, fnum_I_raw,
|
||||
fb_I, alg_I, ams_IV, pms_I } = regch_out;
|
||||
|
||||
jt12_sh #(.width(regch_width),.stages(6)) u_regch(
|
||||
.clk ( clk ),
|
||||
//.rst ( rst ),
|
||||
.din ( regch_in ),
|
||||
.drop ( regch_out )
|
||||
jt12_sh_rst #(.width(regch_width),.stages(num_ch)) u_regch(
|
||||
.clk ( clk ),
|
||||
.clk_en ( clk_en ),
|
||||
.rst ( rst ),
|
||||
.din ( regch_in ),
|
||||
.drop ( regch_out )
|
||||
);
|
||||
|
||||
// RL is on a different register to
|
||||
// have the reset to 1
|
||||
jt12_sh_rst #(.width(2),.stages(6),.rstval(1'b1)) u_regch_rl(
|
||||
.clk ( clk ),
|
||||
// .rst ( rst ),
|
||||
.din ( up_pms_ch ? rl_in : rl ),
|
||||
.drop ( rl )
|
||||
);
|
||||
generate
|
||||
if( num_ch==6 ) begin
|
||||
// RL is on a different register to
|
||||
// have the reset to 1
|
||||
wire [1:0] rl_in = din[7:6];
|
||||
jt12_sh_rst #(.width(2),.stages(num_ch),.rstval(1'b1)) u_regch_rl(
|
||||
.clk ( clk ),
|
||||
.clk_en ( clk_en ),
|
||||
.rst ( rst ),
|
||||
.din ( up_pms_ch ? rl_in : rl ),
|
||||
.drop ( rl )
|
||||
);
|
||||
end else begin // YM2203 has no stereo output
|
||||
assign rl=2'b11;
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user