cleanup gs signals

This commit is contained in:
Eugene Lozovoy
2024-09-10 13:04:42 +03:00
parent 8e70b03d19
commit bfb0352188
3 changed files with 150 additions and 198 deletions

View File

@ -71,9 +71,6 @@ localparam CONF_STR = {
"TSConf;;", "TSConf;;",
"O12,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;", "O12,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
"-;", "-;",
"O34,Stereo mix,None,25%,50%,100%;",
"OST,General Sound,512KB,1MB,2MB;",
"-;",
"OU,CPU Type,NMOS,CMOS;", "OU,CPU Type,NMOS,CMOS;",
"O67,CPU Speed,3.5MHz,7MHz,14MHz;", "O67,CPU Speed,3.5MHz,7MHz,14MHz;",
"O8,CPU Cache,On,Off;", "O8,CPU Cache,On,Off;",
@ -341,12 +338,6 @@ tsconf tsconf
.SD_CLK(sdclk), .SD_CLK(sdclk),
.SD_CS_N(sdss), .SD_CS_N(sdss),
.GS_ADDR(gs_mem_addr),
.GS_DI(gs_mem_din),
.GS_DO(gs_mem_dout | gs_mem_mask),
.GS_RD(gs_mem_rd),
.GS_WR(gs_mem_wr),
.GS_WAIT(~gs_mem_ready),
.SOUND_L(SOUND_L), .SOUND_L(SOUND_L),
.SOUND_R(SOUND_R), .SOUND_R(SOUND_R),
@ -367,34 +358,6 @@ tsconf tsconf
.loader_wr(ioctl_wr && ioctl_download && !ioctl_index && !ioctl_addr[24:16]) .loader_wr(ioctl_wr && ioctl_download && !ioctl_index && !ioctl_addr[24:16])
); );
wire [20:0] gs_mem_addr;
wire [7:0] gs_mem_dout;
wire [7:0] gs_mem_din;
wire gs_mem_rd;
wire gs_mem_wr;
wire gs_mem_ready;
reg [7:0] gs_mem_mask;
always_comb begin
gs_mem_mask = 0;
case(status[29:28])
0: if(gs_mem_addr[20:19]) gs_mem_mask = 8'hFF;
1: if(gs_mem_addr[20]) gs_mem_mask = 8'hFF;
2,3: gs_mem_mask = 0;
endcase
end
// ddram ddram
// (
// .*,
// .addr(gs_mem_addr),
// .dout(gs_mem_dout),
// .din(gs_mem_din),
// .we(gs_mem_wr),
// .rd(gs_mem_rd),
// .ready(gs_mem_ready)
// );
reg VSync, HSync; reg VSync, HSync;
always @(posedge clk_sys) begin always @(posedge clk_sys) begin

View File

@ -66,7 +66,7 @@
*/ */
module gs #(parameter ROMFILE="gs105b.mif") module gs
( (
input RESET, input RESET,
input CLK, input CLK,
@ -85,6 +85,7 @@ module gs #(parameter ROMFILE="gs105b.mif")
output MEM_RD, output MEM_RD,
output MEM_WR, output MEM_WR,
input MEM_WAIT, input MEM_WAIT,
output MEM_ROM,
output [14:0] OUTL, output [14:0] OUTL,
output [14:0] OUTR output [14:0] OUTR
@ -170,7 +171,7 @@ end
reg [5:0] port_00; reg [5:0] port_00;
reg [7:0] port_03; reg [7:0] port_03;
reg signed [6:0] port_06, port_07, port_08, port_09; reg signed [6:0] port_06 = 0, port_07 = 0, port_08 = 0, port_09 = 0;
reg signed [7:0] ch_a, ch_b, ch_c, ch_d; reg signed [7:0] ch_a, ch_b, ch_c, ch_d;
always @(posedge CLK) begin always @(posedge CLK) begin
@ -190,44 +191,33 @@ always @(posedge CLK) begin
endcase endcase
end end
if (~cpu_mreq_n && ~cpu_rd_n && cpu_a_bus[15:13] == 3) begin if (~cpu_mreq_n && ~cpu_rd_n && cpu_a_bus[15:13] == 3 && ~MEM_WAIT) begin
case(cpu_a_bus[9:8]) case(cpu_a_bus[9:8])
0: ch_a <= {~mem_do[7],mem_do[6:0]}; 0: ch_a <= {~MEM_DO[7],MEM_DO[6:0]};
1: ch_b <= {~mem_do[7],mem_do[6:0]}; 1: ch_b <= {~MEM_DO[7],MEM_DO[6:0]};
2: ch_c <= {~mem_do[7],mem_do[6:0]}; 2: ch_c <= {~MEM_DO[7],MEM_DO[6:0]};
3: ch_d <= {~mem_do[7],mem_do[6:0]}; 3: ch_d <= {~MEM_DO[7],MEM_DO[6:0]};
endcase endcase
end end
end end
end end
wire [7:0] cpu_di_bus = wire [7:0] cpu_di_bus =
(~cpu_mreq_n && ~cpu_rd_n && !page_addr[5:1]) ? mem_do :
(~cpu_mreq_n && ~cpu_rd_n) ? MEM_DO : (~cpu_mreq_n && ~cpu_rd_n) ? MEM_DO :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 1) ? port_BB : (~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 1) ? port_BB :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 2) ? port_B3 : (~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 2) ? port_B3 :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {bit7, 6'b111111, bit0} : (~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {bit7, 6'b111111, bit0} :
8'hFF; 8'hFF;
wire mem_wr = ~cpu_wr_n & ~cpu_mreq_n & |page_addr;
wire mem_rd = ~cpu_rd_n & ~cpu_mreq_n;
wire [5:0] page_addr = cpu_a_bus[15] ? port_00 : cpu_a_bus[14]; wire [5:0] page_addr = cpu_a_bus[15] ? port_00 : cpu_a_bus[14];
assign MEM_ADDR = {page_addr, &cpu_a_bus[15:14], cpu_a_bus[13:0]}; assign MEM_ADDR = {page_addr, &cpu_a_bus[15:14], cpu_a_bus[13:0]};
assign MEM_RD = mem_rd && |page_addr[5:1]; assign MEM_RD = ~cpu_rd_n & ~cpu_mreq_n;
assign MEM_WR = mem_wr && |page_addr[5:1]; assign MEM_WR = ~cpu_wr_n & ~cpu_mreq_n & ~MEM_ROM;
assign MEM_DI = cpu_do_bus; assign MEM_DI = cpu_do_bus;
assign MEM_ROM = ~|page_addr;
wire [7:0] mem_do;
dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE(ROMFILE)) mem
(
.clock(CLK),
.address_a(MEM_ADDR[15:0]),
.wren_a(mem_wr && !page_addr[5:1]),
.data_a(cpu_do_bus),
.q_a(mem_do)
);
reg signed [14:0] out_a,out_b,out_c,out_d; reg signed [14:0] out_a,out_b,out_c,out_d;
always @(posedge CLK) begin always @(posedge CLK) begin

View File

@ -88,14 +88,6 @@ module tsconf
output SD_CLK, output SD_CLK,
output SD_CS_N, output SD_CS_N,
// General Sound
output [20:0] GS_ADDR,
output [7:0] GS_DI,
input [7:0] GS_DO,
output GS_RD,
output GS_WR,
input GS_WAIT,
// Audio // Audio
output [15:0] SOUND_L, output [15:0] SOUND_L,
output [15:0] SOUND_R, output [15:0] SOUND_R,
@ -816,12 +808,19 @@ turbosound SE12
// General Sound // General Sound
wire [20:0] gs_mem_addr;
wire [7:0] gs_mem_di;
wire [7:0] gs_mem_do;
wire gs_mem_rd;
wire gs_mem_wr;
wire gs_mem_wait;
wire [14:0] gs_l; wire [14:0] gs_l;
wire [14:0] gs_r; wire [14:0] gs_r;
wire [7:0] gs_do_bus; wire [7:0] gs_do_bus;
wire gs_sel = ~cpu_iorq_n & cpu_m1_n & (cpu_a_bus[7:4] == 'hB && cpu_a_bus[2:0] == 'h3); wire gs_sel = ~cpu_iorq_n & cpu_m1_n & (cpu_a_bus[7:4] == 'hB && cpu_a_bus[2:0] == 'h3);
gs #("rtl/sound/gs105b.mif") U15 gs U15
( (
.RESET(reset | 1'b1), .RESET(reset | 1'b1),
.CLK(clk), .CLK(clk),
@ -834,12 +833,12 @@ gs #("rtl/sound/gs105b.mif") U15
.WR_n(cpu_wr_n), .WR_n(cpu_wr_n),
.RD_n(cpu_rd_n), .RD_n(cpu_rd_n),
.MEM_ADDR(GS_ADDR), .MEM_ADDR(gs_mem_addr),
.MEM_DI(GS_DI), .MEM_DI(gs_mem_di),
.MEM_DO(GS_DO), .MEM_DO(gs_mem_do),
.MEM_RD(GS_RD), .MEM_RD(gs_mem_rd),
.MEM_WR(GS_WR), .MEM_WR(gs_mem_wr),
.MEM_WAIT(GS_WAIT), .MEM_WAIT(gs_mem_wait),
.OUTL(gs_l), .OUTL(gs_l),
.OUTR(gs_r) .OUTR(gs_r)