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update JT12
This commit is contained in:
Eugene Lozovoy
@ -23,30 +23,35 @@
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module jt12_reg(
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input rst,
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input clk,
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input clk_en,
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input [7:0] din,
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input clk_en /* synthesis direct_enable */,
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input [2:0] ch,
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input [2:0] ch, // channel to update
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input [1:0] op,
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input csm,
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input flag_A,
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input overflow_A,
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input up_keyon,
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// channel udpates
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input [2:0] ch_sel,
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input [7:0] ch_din,
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input up_alg,
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input up_fnumlo,
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// operator updates
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input [7:0] din,
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input up_keyon,
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input up_pms,
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input up_dt1,
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input up_tl,
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input up_ks_ar,
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input up_amen_dr,
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input up_sr,
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input up_sl_rr,
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input up_ssgeg,
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output reg ch6op, // 1 when the operator belongs to CH6
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output reg ch6op, // 1 when the operator belongs to CH6
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output reg [2:0] cur_ch,
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output reg [1:0] cur_op,
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// CH3 Effect-mode operation
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input effect,
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@ -105,8 +110,8 @@ module jt12_reg(
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parameter num_ch=6; // Use only 3 (YM2203/YM2610) or 6 (YM2612/YM2608)
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reg [1:0] next_op, cur_op;
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reg [2:0] next_ch, cur_ch;
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reg [1:0] next_op;
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reg [2:0] next_ch;
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reg last;
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`ifdef SIMULATION
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@ -117,6 +122,8 @@ reg last;
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initial begin
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cur_op = 2'd0;
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cur_ch = 3'd0;
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next_op = 2'd0;
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next_ch = 3'd1;
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last = 1'b0;
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zero = 1'b1;
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end
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@ -155,11 +162,9 @@ assign block_I =( {3{effect_on_s1}} & block_ch3op1 ) |
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( {3{effect_on_s3}} & block_ch3op3 ) |
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( {3{noeffect}} & block_I_raw );
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wire [2:0] ch_II, ch_III, ch_IV, ch_V, ch_VI;
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wire [4:0] req_opch_I = { op, ch };
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wire [4:0] req_opch_II, req_opch_III,
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req_opch_IV, req_opch_V, req_opch_VI;
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req_opch_IV, req_opch_V; //, req_opch_VI;
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jt12_sumch #(.num_ch(num_ch)) u_opch_II ( .chin(req_opch_I ), .chout(req_opch_II ) );
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jt12_sumch #(.num_ch(num_ch)) u_opch_III( .chin(req_opch_II ), .chout(req_opch_III) );
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@ -179,24 +184,6 @@ wire update_op_IV = cur == req_opch_IV;
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// key on/off
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wire [3:0] keyon_op = din[7:4];
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wire [2:0] keyon_ch = din[2:0];
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// channel data
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//wire [1:0] rl_in = din[7:6];
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wire [2:0] fb_in = din[5:3];
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wire [2:0] alg_in = din[2:0];
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wire [2:0] pms_in = din[2:0];
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wire [1:0] ams_in = din[5:4];
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wire [7:0] fnlo_in = din;
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wire update_ch_I = cur_ch == ch;
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wire update_ch_IV = num_ch==6 ?
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{ ~cur_ch[2], cur_ch[1:0]} == ch : // 6 channels
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cur[1:0] == ch[1:0]; // 3 channels
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wire up_alg_ch = up_alg & update_ch_I;
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wire up_fnumlo_ch=up_fnumlo & update_ch_I;
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wire up_pms_ch = up_pms & update_ch_I;
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wire up_ams_ch = up_pms & update_ch_IV;
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always @(*) begin
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// next = cur==5'd23 ? 5'd0 : cur +1'b1;
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@ -216,6 +203,7 @@ always @(posedge clk) begin : up_counter
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end
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end
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`ifndef NOFM
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jt12_kon #(.num_ch(num_ch)) u_kon(
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.rst ( rst ),
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.clk ( clk ),
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@ -325,46 +313,27 @@ assign { tl_IV, dt1_I, mul_II, ks_II,
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// memory for CH registers
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// Block/fnum data is latched until fnum low byte is written to
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// Trying to synthesize this memory as M-9K RAM in Altera devices
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// turns out worse in terms of resource utilization. Probably because
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// this memory is already very small. It is better to leave it as it is.
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localparam regch_width=25;
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wire [regch_width-1:0] regch_out;
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wire [regch_width-1:0] regch_in = {
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up_fnumlo_ch? { latch_fnum, fnlo_in } : { block_I_raw, fnum_I_raw }, // 14
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up_alg_ch ? { fb_in, alg_in } : { fb_I, alg_I },//3+3
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up_ams_ch ? ams_in : ams_IV, //2
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up_pms_ch ? pms_in : pms_I //3
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};
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jt12_reg_ch #(.NUM_CH(num_ch)) u_regch(
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.rst ( rst ),
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.clk ( clk ),
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.cen ( clk_en ),
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.din ( ch_din ),
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assign { block_I_raw, fnum_I_raw,
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fb_I, alg_I, ams_IV, pms_I } = regch_out;
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.up_ch ( ch_sel ),
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.latch_fnum ( latch_fnum ),
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.up_fnumlo ( up_fnumlo ),
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.up_alg ( up_alg ),
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.up_pms ( up_pms ),
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jt12_sh_rst #(.width(regch_width),.stages(num_ch)) u_regch(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.rst ( rst ),
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.din ( regch_in ),
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.drop ( regch_out )
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.ch ( next_ch ), // next active channel
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.block ( block_I_raw ),
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.fnum ( fnum_I_raw ),
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.fb ( fb_I ),
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.alg ( alg_I ),
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.rl ( rl ),
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.ams_IV ( ams_IV ),
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.pms ( pms_I )
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);
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generate
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if( num_ch==6 ) begin
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// RL is on a different register to
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// have the reset to 1
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wire [1:0] rl_in = din[7:6];
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jt12_sh_rst #(.width(2),.stages(num_ch),.rstval(1'b1)) u_regch_rl(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.rst ( rst ),
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.din ( up_pms_ch ? rl_in : rl ),
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.drop ( rl )
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);
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end else begin // YM2203 has no stereo output
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assign rl=2'b11;
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end
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endgenerate
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`endif
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endmodule
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