diff --git a/src/sound/soundrive.vhd b/src/sound/soundrive.vhd
index 456c288..8df9b78 100644
--- a/src/sound/soundrive.vhd
+++ b/src/sound/soundrive.vhd
@@ -1,7 +1,7 @@
 -------------------------------------------------------------------[27.10.2011]
 -- Soundrive 1.05
 -------------------------------------------------------------------------------
--- V0.1 	05.10.2011	ïåðâàÿ âåðñèÿ
+-- V0.1 	05.10.2011	������ ������
 
 -- SOUNDRIVE 1.05 PORTS mode 1
 -- #0F = left channel A (stereo covox channel 1)
@@ -17,25 +17,21 @@ use IEEE.NUMERIC_STD.ALL;
  
 entity soundrive is
 	Port ( 
-		RESET	: in std_logic;
-		CLK		: in std_logic;
-		CS		: in std_logic;
-		A		: in std_logic_vector(7 downto 0);
-		DI		: in std_logic_vector(7 downto 0);
-		WR_n	: in std_logic;
-		IORQ_n	: in std_logic;
-		DOS		: in std_logic;
+		RESET	: in  std_logic;
+		CLK	: in  std_logic;
+		CS		: in  std_logic;
+		A		: in  std_logic_vector(7 downto 0);
+		DI		: in  std_logic_vector(7 downto 0);
+		WR_n	: in  std_logic;
+		IORQ_n: in  std_logic;
+		DOS	: in  std_logic;
 		OUTA	: out std_logic_vector(7 downto 0);
 		OUTB	: out std_logic_vector(7 downto 0);
 		OUTC	: out std_logic_vector(7 downto 0);
 		OUTD	: out std_logic_vector(7 downto 0));
 end soundrive;
- 
+
 architecture soundrive_unit of soundrive is
-	signal outa_reg : std_logic_vector (7 downto 0);
-	signal outb_reg : std_logic_vector (7 downto 0);
-	signal outc_reg : std_logic_vector (7 downto 0);
-	signal outd_reg : std_logic_vector (7 downto 0);
 begin
 	process (CLK, RESET, CS)
 	begin
@@ -44,17 +40,12 @@ begin
 			outb <= (others => '0');
 			outc <= (others => '0');
 			outd <= (others => '0');
-		elsif CLK'event and CLK = '1' then
-			if A = X"0F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then
-				outa <= DI;
-			elsif A = X"1F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then
-				outb <= DI;
-			elsif A = X"4F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then
-				outc <= DI;
-			elsif A = X"5F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then
-				outd <= DI;
-			elsif A = X"FB" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then
-				outd <= DI;
+		elsif rising_edge(CLK) then
+			if    A = X"0F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outa <= DI;
+			elsif A = X"1F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outb <= DI;
+			elsif A = X"4F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outc <= DI;
+			elsif A = X"5F" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outd <= DI;
+			elsif A = X"FB" and IORQ_n = '0' and WR_n = '0' and DOS = '0' then outd <= DI;
 			end if;
 		end if;
 	end process;