mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
timings-related fixes
This commit is contained in:
Eugene Lozovoy
49
TSConf.qsf
49
TSConf.qsf
@ -120,7 +120,7 @@ set_location_assignment PIN_66 -to SDRAM_nWE
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set_location_assignment PIN_59 -to SDRAM_nCS
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set_location_assignment PIN_33 -to SDRAM_CKE
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set_location_assignment PIN_43 -to SDRAM_CLK
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set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
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set_location_assignment PIN_90 -to SPI_SS4
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# Classic Timing Assignments
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# ==========================
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@ -139,14 +139,14 @@ set_global_assignment -name SAVE_DISK_SPACE OFF
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# Fitter Assignments
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# ==================
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set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
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set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE REALISTIC
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
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set_global_assignment -name DEVICE EP3C25E144C8
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set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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@ -160,6 +160,12 @@ set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS R
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name SEED 0
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set_global_assignment -name SYNTHESIS_SEED 0
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set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
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set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION"
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set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "NORMAL COMPILATION"
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set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
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# Assembler Assignments
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# =====================
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@ -168,7 +174,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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# SignalTap II Assignments
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# ========================
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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# Power Estimation Assignments
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# ============================
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@ -268,43 +274,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TX
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
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set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
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# start DESIGN_PARTITION(Top)
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# ---------------------------
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# Incremental Compilation Assignments
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# ===================================
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(zxspectrum)
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# ----------------------
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_id_verilog.tcl"
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set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
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set_global_assignment -name SEED 0
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
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set_global_assignment -name QIP_FILE pll.qip
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set_global_assignment -name QIP_FILE files.qip
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set_global_assignment -name QIP_FILE "mist-modules/mist.qip"
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set_location_assignment PIN_90 -to SPI_SS4
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
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set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
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set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_global_assignment -name ECO_OPTIMIZE_TIMING ON
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set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
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set_global_assignment -name SEED 1
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source sys/sys.tcl
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source sys/sys_analog.tcl
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source files.qip
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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11
TSConf.sdc
11
TSConf.sdc
@ -12,19 +12,20 @@ derive_clock_uncertainty
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# Clock groups
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set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
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# SDRAM delays
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# SDRAM
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set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -max 6.4 [get_ports SDRAM_DQ[*]]
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set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -min 3.2 [get_ports SDRAM_DQ[*]]
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# SDRAM: max(tCMS, tAS, tDS) = 1.5ns ; max(tCMH, tAH, tDH) = 0.8ns
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports SDRAM_CLK] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
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#SDRAM_CLK to internal memory clock
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#set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2
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# SDRAM_CLK to internal memory clock
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set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -setup 2
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# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 0 [get_ports {VGA_*}]
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set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min -5 [get_ports {VGA_*}]
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set_multicycle_path -to [get_ports {VGA_*}] -setup 5
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set_multicycle_path -to [get_ports {VGA_*}] -hold 4
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59
TSConf.srf
59
TSConf.srf
@ -1,29 +1,30 @@
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{ "" "" "" "Vip.Mixer: The MixerII register map changed in ACDS v16.0. Please refer to the VIP User Guide for details." { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_sys: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_warm: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_cold: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Video_Output.control: Interrupt sender control.av_mm_control_interrupt is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.Video_Output: Interrupt sender Video_Output.status_update_irq is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram1_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram2_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Port \"trs\" on the entity instantiation of \"statemachine\" is connected to a signal of width 2. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_cvo_mode_banks.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
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{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
|
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{ "" "" "" "Vip.Mixer: The MixerII register map changed in ACDS v16.0. Please refer to the VIP User Guide for details." { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
|
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{ "" "" "" "Vip.Reset_Source.reset_sys: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_warm: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Vip.Reset_Source.reset_cold: Associated reset sinks not declared" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Vip.Video_Output.control: Interrupt sender control.av_mm_control_interrupt is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
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{ "" "" "" "Vip.Video_Output: Interrupt sender Video_Output.status_update_irq is not connected to an interrupt receiver" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
|
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{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram1_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram2_data but not its associated reset interface. Export the driver(s) of HPS.h2f_reset" { } { } 0 12251 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { } 0 12030 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"trs\" on the entity instantiation of \"statemachine\" is connected to a signal of width 2. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 292013 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_cvo_mode_banks.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "altera_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "altera_cyclonev_pll.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "altera_pll_reconfig_core.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "RST port on the PLL is not properly connected" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
|
||||
23
TSConf.sv
23
TSConf.sv
@ -108,13 +108,26 @@ assign CMOSCfg[27:25]= status[27:25] + 1'd1;
|
||||
|
||||
//////////////////// CLOCKS ///////////////////
|
||||
wire clk_sys;
|
||||
wire locked;
|
||||
|
||||
wire clk_ram;
|
||||
pll pll
|
||||
(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clk_sys),
|
||||
.locked(locked)
|
||||
.c0(clk_ram),
|
||||
.c1(clk_sys),
|
||||
.locked()
|
||||
);
|
||||
|
||||
altclkctrl
|
||||
#(
|
||||
.number_of_clocks(1),
|
||||
.clock_type("External Clock Output"),
|
||||
.ena_register_mode("none"),
|
||||
.intended_device_family("Cyclone III")
|
||||
)
|
||||
altclkctrl
|
||||
(
|
||||
.inclk(clk_ram),
|
||||
.outclk(SDRAM_CLK)
|
||||
);
|
||||
|
||||
reg ce_28m;
|
||||
@ -312,7 +325,7 @@ tsconf tsconf
|
||||
.SDRAM_nRAS(SDRAM_nRAS),
|
||||
.SDRAM_CKE(SDRAM_CKE),
|
||||
.SDRAM_nCS(SDRAM_nCS),
|
||||
.SDRAM_CLK(SDRAM_CLK),
|
||||
// .SDRAM_CLK(SDRAM_CLK),
|
||||
|
||||
.VGA_R(R),
|
||||
.VGA_G(G),
|
||||
|
||||
52
pll.v
52
pll.v
@ -39,23 +39,27 @@
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire5 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire sub_wire3 = inclk0;
|
||||
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire4),
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
@ -97,7 +101,11 @@ module pll (
|
||||
altpll_component.clk0_divide_by = 9,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 28,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk0_phase_shift = "7440",
|
||||
altpll_component.clk1_divide_by = 9,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 28,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
@ -130,7 +138,7 @@ module pll (
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
@ -167,12 +175,15 @@ endmodule
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "84.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "84.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@ -193,18 +204,26 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "84.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "84.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "225.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
@ -227,11 +246,14 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
@ -239,7 +261,11 @@ endmodule
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "28"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "7440"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "28"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
@ -271,7 +297,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
@ -290,11 +316,13 @@ endmodule
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
|
||||
@ -1,3 +1,18 @@
|
||||
// READ 25 26 27 21 22 23 24
|
||||
// RAS CAS read
|
||||
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
|
||||
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
|
||||
// T0 T1 T2 T3 T4 T5 T6
|
||||
// 5.95ns ACT READ DQDQDQDQD
|
||||
// tAC=6 tOH=3
|
||||
//
|
||||
// WRITE 25 26 27 22 23 24
|
||||
// RAS CASWEDQ
|
||||
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
|
||||
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
|
||||
// T0 T1 T2 T3 T4 T5
|
||||
// 5.95ns ACT WRITE
|
||||
//
|
||||
|
||||
module sdram
|
||||
(
|
||||
|
||||
@ -888,8 +888,10 @@ compressor compressor
|
||||
//-----------------------------------------------------------------------------
|
||||
// Global
|
||||
//-----------------------------------------------------------------------------
|
||||
wire reset = COLD_RESET | WARM_RESET | key_reset;
|
||||
reg reset;
|
||||
assign RESET_OUT = reset;
|
||||
always @(posedge clk)
|
||||
reset <= COLD_RESET | WARM_RESET | key_reset;
|
||||
|
||||
// CPU interface
|
||||
assign cpu_di_bus =
|
||||
|
||||
Reference in New Issue
Block a user