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timings-related fixes

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Eugene Lozovoy
2024-09-10 11:19:14 +03:00
parent b575eed412
commit a335568fb0
7 changed files with 572 additions and 535 deletions
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15
rtl/memory/sdram.v
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@ -1,3 +1,18 @@
// READ 25 26 27 21 22 23 24
// RAS CAS read
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// T0 T1 T2 T3 T4 T5 T6
// 5.95ns ACT READ DQDQDQDQD
// tAC=6 tOH=3
//
// WRITE 25 26 27 22 23 24
// RAS CASWEDQ
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// T0 T1 T2 T3 T4 T5
// 5.95ns ACT WRITE
//
module sdram
(