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Update sys.

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This commit is contained in:
sorgelig
2019-07-12 04:24:12 +08:00
parent fa444aec03
commit 9695397185
31 changed files with 2207 additions and 1365 deletions
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6
sys/sys_top.sdc
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@ -7,7 +7,7 @@ create_clock -period 10.0 [get_pins -compatibility_mode spi|sclk_out] -name spi_
derive_pll_clocks
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
@ -15,8 +15,8 @@ derive_clock_uncertainty
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]