mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
Update sys. Persistent mounted image.
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@ -10,10 +10,7 @@
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`timescale 1ns / 1ps
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//
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// LINE_LENGTH: Length of display line in pixels
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// Usually it's length from HSync to HSync.
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// May be less if line_start is used.
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//
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// LINE_LENGTH: Length of display line in pixels when HBlank = 0;
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// HALF_DEPTH: If =1 then color dept is 4 bits per component
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//
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// altera message_off 10720
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@ -47,6 +44,12 @@ module video_mixer
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input HBlank,
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input VBlank,
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// Freeze engine
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// HDMI: displays last frame
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// VGA: black screen with HSync and VSync
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input HDMI_FREEZE,
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output freeze_sync,
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// video output signals
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output reg [7:0] VGA_R,
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output reg [7:0] VGA_G,
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@ -60,19 +63,43 @@ localparam DWIDTH = HALF_DEPTH ? 3 : 7;
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localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH;
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localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH;
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wire frz_hs, frz_vs;
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wire frz_hbl, frz_vbl;
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video_freezer freezer
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(
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.clk(CLK_VIDEO),
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.freeze(HDMI_FREEZE),
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.hs_in(HSync),
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.vs_in(VSync),
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.hbl_in(HBlank),
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.vbl_in(VBlank),
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.sync(freeze_sync),
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.hs_out(frz_hs),
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.vs_out(frz_vs),
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.hbl_out(frz_hbl),
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.vbl_out(frz_vbl)
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);
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reg frz;
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always @(posedge CLK_VIDEO) begin
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reg frz1;
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frz1 <= HDMI_FREEZE;
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frz <= frz1;
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end
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generate
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if(GAMMA && HALF_DEPTH) begin
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wire [7:0] R_in = {R,R};
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wire [7:0] G_in = {G,G};
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wire [7:0] B_in = {B,B};
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wire [7:0] R_in = frz ? 8'd0 : {R,R};
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wire [7:0] G_in = frz ? 8'd0 : {G,G};
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wire [7:0] B_in = frz ? 8'd0 : {B,B};
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end else begin
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wire [DWIDTH:0] R_in = R;
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wire [DWIDTH:0] G_in = G;
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wire [DWIDTH:0] B_in = B;
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wire [DWIDTH:0] R_in = frz ? 1'd0 : R;
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wire [DWIDTH:0] G_in = frz ? 1'd0 : G;
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wire [DWIDTH:0] B_in = frz ? 1'd0 : B;
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end
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endgenerate
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wire hs_g, vs_g;
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wire hb_g, vb_g;
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wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma;
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@ -90,10 +117,10 @@ generate
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.gamma_wr_addr(gamma_bus[17:8]),
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.gamma_value(gamma_bus[7:0]),
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.HSync(HSync),
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.VSync(VSync),
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.HBlank(HBlank),
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.VBlank(VBlank),
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.HSync(frz_hs),
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.VSync(frz_vs),
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.HBlank(frz_hbl),
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.VBlank(frz_vbl),
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.RGB_in({R_in,G_in,B_in}),
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.HSync_out(hs_g),
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@ -105,7 +132,7 @@ generate
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end else begin
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assign gamma_bus[21] = 0;
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assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in};
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assign {hs_g, vs_g, hb_g, vb_g} = {HSync, VSync, HBlank, VBlank};
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assign {hs_g, vs_g, hb_g, vb_g} = {frz_hs, frz_vs, frz_hbl, frz_vbl};
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end
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endgenerate
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