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add fifo for ps/2 keyboard scancodes (#1)

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This commit is contained in:
Eugene Lozovoy
2024-10-03 20:36:55 +03:00
parent 858e4a2a61
commit 8a1898cf8e
3 changed files with 354 additions and 269 deletions
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96
rtl/periph/keyboard.v
View File

@ -6,6 +6,8 @@ module keyboard
output [4:0] keyb, output [4:0] keyb,
output reg key_reset, output reg key_reset,
output reg [7:0] scancode, output reg [7:0] scancode,
input scancode_ack,
input scancode_clr,
input [10:0] ps2_key, input [10:0] ps2_key,
input [1:0] cfg_joystick1, input [1:0] cfg_joystick1,
input [1:0] cfg_joystick2, input [1:0] cfg_joystick2,
@ -93,10 +95,10 @@ always @(posedge clk) begin
end end
2'b11: begin // Cursor 2'b11: begin // Cursor
case (joys_chn) case (joys_chn)
0: {strobe, press, code} <= {1'b1, joys[0 ], 9'h74}; // Right | Right 0: {strobe, press, code} <= {1'b1, joys[0 ], 9'h174}; // Right | Right
1: {strobe, press, code} <= {1'b1, joys[1 ], 9'h6b}; // Left | Left 1: {strobe, press, code} <= {1'b1, joys[1 ], 9'h16b}; // Left | Left
2: {strobe, press, code} <= {1'b1, joys[2 ], 9'h72}; // Down | Down 2: {strobe, press, code} <= {1'b1, joys[2 ], 9'h172}; // Down | Down
3: {strobe, press, code} <= {1'b1, joys[3 ], 9'h75}; // Up | Up 3: {strobe, press, code} <= {1'b1, joys[3 ], 9'h175}; // Up | Up
4: {strobe, press, code} <= {1'b1, joys[4 ], 9'h5a}; // Fire 1 | Enter 4: {strobe, press, code} <= {1'b1, joys[4 ], 9'h5a}; // Fire 1 | Enter
5: {strobe, press, code} <= {1'b1, joys[5 ], 9'h0d}; // Fire 2 | Tab 5: {strobe, press, code} <= {1'b1, joys[5 ], 9'h0d}; // Fire 2 | Tab
6: {strobe, press, code} <= {1'b1, joys[6 ], 9'h29}; // Fire 3 | Space 6: {strobe, press, code} <= {1'b1, joys[6 ], 9'h29}; // Fire 3 | Space
@ -131,10 +133,10 @@ always @(posedge clk) begin
end end
2'b11: begin // Cursor 2'b11: begin // Cursor
case (joys_chn) case (joys_chn)
8: {strobe, press, code} <= {1'b1, joys[8 ], 9'h74}; // Right | Right 8: {strobe, press, code} <= {1'b1, joys[8 ], 9'h174}; // Right | Right
9: {strobe, press, code} <= {1'b1, joys[9 ], 9'h6b}; // Left | Left 9: {strobe, press, code} <= {1'b1, joys[9 ], 9'h16b}; // Left | Left
10: {strobe, press, code} <= {1'b1, joys[10], 9'h72}; // Down | Down 10: {strobe, press, code} <= {1'b1, joys[10], 9'h172}; // Down | Down
11: {strobe, press, code} <= {1'b1, joys[11], 9'h75}; // Up | Up 11: {strobe, press, code} <= {1'b1, joys[11], 9'h175}; // Up | Up
12: {strobe, press, code} <= {1'b1, joys[12], 9'h5a}; // Fire 1 | Enter 12: {strobe, press, code} <= {1'b1, joys[12], 9'h5a}; // Fire 1 | Enter
13: {strobe, press, code} <= {1'b1, joys[13], 9'h0d}; // Fire 2 | Tab 13: {strobe, press, code} <= {1'b1, joys[13], 9'h0d}; // Fire 2 | Tab
14: {strobe, press, code} <= {1'b1, joys[14], 9'h29}; // Fire 3 | Space 14: {strobe, press, code} <= {1'b1, joys[14], 9'h29}; // Fire 3 | Space
@ -157,14 +159,9 @@ always @(posedge clk or posedge reset) begin
keys[6] <= 5'b11111; keys[6] <= 5'b11111;
keys[7] <= 5'b11111; keys[7] <= 5'b11111;
key_reset <= 0; key_reset <= 0;
scancode <= 0;
end end
else begin else begin
if (strobe) begin if (strobe) begin
if (press)
scancode <= code[7:0];
else
scancode <= 8'hFF;
case (code[7:0]) case (code[7:0])
8'h12: keys[0][0] <= ~press; // Left shift (CAPS SHIFT) 8'h12: keys[0][0] <= ~press; // Left shift (CAPS SHIFT)
8'h59: keys[0][0] <= ~press; // Right shift (CAPS SHIFT) 8'h59: keys[0][0] <= ~press; // Right shift (CAPS SHIFT)
@ -297,4 +294,77 @@ always @(posedge clk or posedge reset) begin
end end
end end
reg fifo_rdreq;
wire [9:0] fifo_q;
wire fifo_empty;
scfifo
#(
.lpm_width(10),
.lpm_widthu(6),
.lpm_numwords(64),
.lpm_showahead("OFF"),
.overflow_checking("ON"),
.underflow_checking("OFF"),
.add_ram_output_register("ON")
)
fifo_scancodes
(
.clock(clk),
.data({~press, code}),
.wrreq(strobe),
.rdreq(fifo_rdreq),
.sclr(scancode_clr),
.q(fifo_q),
.empty(fifo_empty)
);
reg [1:0] step = 0;
always @(posedge clk) begin
fifo_rdreq <= 0;
scancode <= 0;
case (step)
2'd0: begin
if (!fifo_empty) begin
fifo_rdreq <= 1'b1;
step <= step + 1'b1;
end
end
2'd1: begin
if (fifo_q[8])
scancode <= 8'hE0;
else if (fifo_q[9])
scancode <= 8'hF0;
else
scancode <= fifo_q[7:0];
if (scancode_ack)
step <= step + 1'b1;
end
2'd2: begin
if (fifo_q[9] && fifo_q[8])
scancode <= 8'hF0;
else if (fifo_q[8] || fifo_q[9])
scancode <= fifo_q[7:0];
if (scancode_ack)
step <= step + 1'b1;
end
2'd3: begin
if (fifo_q[9] && fifo_q[8])
scancode <= fifo_q[7:0];
if (scancode_ack)
step <= step + 1'b1;
end
endcase
if (scancode_clr)
step <= 0;
end
endmodule endmodule

100
rtl/periph/mc146818a.v
View File

@ -1,9 +1,3 @@
//-----------------------------------------------------------------[18.10.2014]
// MC146818A REAL-TIME CLOCK PLUS RAM
//-----------------------------------------------------------------------------
// V0.1 05.10.2011 Initial version
// V0.2 06.09.2014 Added General Purpose RAM
module mc146818a module mc146818a
( (
input RESET, input RESET,
@ -13,11 +7,14 @@ module mc146818a
input [64:0] RTC, input [64:0] RTC,
input [7:0] KEYSCANCODE, input [7:0] KEYSCANCODE,
output reg KEYSCANCODE_ACK,
output reg KEYSCANCODE_CLR,
input RD,
input WR, input WR,
input [7:0] A, input [7:0] A,
input [7:0] DI, input [7:0] DI,
output [7:0] DO, output reg [7:0] DO,
input loader_WR, input loader_WR,
input [7:0] loader_A, input [7:0] loader_A,
@ -41,34 +38,44 @@ reg [7:0] a_reg; // 0A
reg [7:0] b_reg = 8'b00000010; // 0B reg [7:0] b_reg = 8'b00000010; // 0B
reg [7:0] c_reg; // 0C reg [7:0] c_reg; // 0C
wire [7:0] CMOS_Dout;
reg [7:0] Dout;
assign DO = Dout; reg keyrd_enable = 0;
reg keyrd = 0;
always @(*) begin always @(posedge CLK) begin
case (A[7:0]) KEYSCANCODE_ACK <= !RD && keyrd;
8'h00 : Dout <= seconds_reg; keyrd <= keyrd_enable && RD && CS && A[7:4] == 4'hf;
8'h01 : Dout <= seconds_alarm_reg;
8'h02 : Dout <= minutes_reg;
8'h03 : Dout <= minutes_alarm_reg;
8'h04 : Dout <= hours_reg;
8'h05 : Dout <= hours_alarm_reg;
8'h06 : Dout <= weeks_reg;
8'h07 : Dout <= days_reg;
8'h08 : Dout <= month_reg;
8'h09 : Dout <= year_reg;
8'h0a : Dout <= a_reg;
8'h0b : Dout <= b_reg;
8'h0c : Dout <= c_reg;
8'h0d : Dout <= 8'b10000000;
8'hf0 : Dout <= KEYSCANCODE;
default: Dout <= CMOS_Dout;
endcase
end end
wire [7:0] CMOS_Dout;
always @(posedge CLK) begin always @(posedge CLK) begin
if (RD & CS) begin
casez (A[7:0])
8'h00 : DO <= seconds_reg;
8'h01 : DO <= seconds_alarm_reg;
8'h02 : DO <= minutes_reg;
8'h03 : DO <= minutes_alarm_reg;
8'h04 : DO <= hours_reg;
8'h05 : DO <= hours_alarm_reg;
8'h06 : DO <= weeks_reg;
8'h07 : DO <= days_reg;
8'h08 : DO <= month_reg;
8'h09 : DO <= year_reg;
8'h0a : DO <= a_reg;
8'h0b : DO <= b_reg;
8'h0c : DO <= c_reg;
8'h0d : DO <= 8'b10000000;
8'hf? : DO <= KEYSCANCODE;
default: DO <= CMOS_Dout;
endcase
end
end
always @(posedge CLK) begin
KEYSCANCODE_CLR <= 1'b0;
if (RTC[62] && !b_reg[7]) begin if (RTC[62] && !b_reg[7]) begin
seconds_reg <= RTC[7:0]; seconds_reg <= RTC[7:0];
minutes_reg <= RTC[15:8]; minutes_reg <= RTC[15:8];
@ -82,19 +89,18 @@ always @(posedge CLK) begin
if (RESET) b_reg <= 8'b00000010; if (RESET) b_reg <= 8'b00000010;
else if (WR & CS) begin else if (WR & CS) begin
/* casez (A[7:0])
case (A[7:0]) 8'h00 : seconds_reg <= DI;
0 : seconds_reg <= DI; 8'h01 : seconds_alarm_reg <= DI;
1 : seconds_alarm_reg <= DI; 8'h02 : minutes_reg <= DI;
2 : minutes_reg <= DI; 8'h03 : minutes_alarm_reg <= DI;
3 : minutes_alarm_reg <= DI; 8'h04 : hours_reg <= DI;
4 : hours_reg <= DI; 8'h05 : hours_alarm_reg <= DI;
5 : hours_alarm_reg <= DI; 8'h06 : weeks_reg <= DI;
6 : weeks_reg <= DI; 8'h07 : days_reg <= DI;
7 : days_reg <= DI; 8'h08 : month_reg <= DI;
8 : month_reg <= DI; 8'h09 : year_reg <= DI;
9 : year_reg <= DI; 8'h0b : begin
11 : begin
b_reg <= DI; b_reg <= DI;
if (b_reg[2] == 1'b0) begin // BCD to BIN convertion if (b_reg[2] == 1'b0) begin // BCD to BIN convertion
if (DI[4] == 1'b0) leap_reg <= DI[1:0]; if (DI[4] == 1'b0) leap_reg <= DI[1:0];
@ -104,8 +110,9 @@ always @(posedge CLK) begin
leap_reg <= DI[1:0]; leap_reg <= DI[1:0];
end end
end end
8'h0c : KEYSCANCODE_CLR <= DI[0];
8'hf? : keyrd_enable <= (DI == 8'd2)? 1'b1 : 1'b0;
endcase endcase
*/
end end
if (RESET) begin if (RESET) begin
@ -189,7 +196,8 @@ always @(posedge CLK) begin
end end
end end
end end
end else begin end
else begin
// DM binary data mode // DM binary data mode
if (seconds_reg != 8'h3B) seconds_reg <= seconds_reg + 1'd1; if (seconds_reg != 8'h3B) seconds_reg <= seconds_reg + 1'd1;
else begin else begin

7
rtl/tsconf.v
View File

@ -926,6 +926,8 @@ module tsconf
// PS/2 Keyboard // PS/2 Keyboard
wire key_reset; wire key_reset;
wire [7:0] key_scancode; wire [7:0] key_scancode;
wire key_scancode_ack;
wire key_scancode_clr;
keyboard keyboard keyboard keyboard
( (
@ -935,6 +937,8 @@ module tsconf
.keyb(kbd_port_data), .keyb(kbd_port_data),
.key_reset(key_reset), .key_reset(key_reset),
.scancode(key_scancode), .scancode(key_scancode),
.scancode_ack(key_scancode_ack),
.scancode_clr(key_scancode_clr),
.ps2_key(PS2_KEY), .ps2_key(PS2_KEY),
.cfg_joystick1(CFG_JOYSTICK1), .cfg_joystick1(CFG_JOYSTICK1),
.cfg_joystick2(CFG_JOYSTICK2), .cfg_joystick2(CFG_JOYSTICK2),
@ -973,6 +977,9 @@ module tsconf
.CS(1), .CS(1),
.RTC(RTC), .RTC(RTC),
.KEYSCANCODE(key_scancode), .KEYSCANCODE(key_scancode),
.KEYSCANCODE_ACK(key_scancode_ack),
.KEYSCANCODE_CLR(key_scancode_clr),
.RD(wait_start_gluclock & ~rd_n),
.WR(wait_start_gluclock & ~wr_n), .WR(wait_start_gluclock & ~wr_n),
.A(wait_addr), .A(wait_addr),
.DI(d), .DI(d),