uzix/TSConf_MiST
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tune sdram

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This commit is contained in:
Eugene Lozovoy
2024-09-18 19:12:28 +03:00
parent a718abd9eb
commit 8909ef759b
2 changed files with 12 additions and 9 deletions
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6
pll.v
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@ -101,7 +101,7 @@ module pll (
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 28,
altpll_component.clk0_phase_shift = "7440",
altpll_component.clk0_phase_shift = "-1488",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 28,
@ -219,7 +219,7 @@ endmodule
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "225.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-45.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
@ -261,7 +261,7 @@ endmodule
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "28"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "7440"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-1488"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "28"

15
rtl/dram/sdram.v
View File

@ -1,13 +1,13 @@
// 25 26 27 28 29 30 31 20 21 22 23 24 25
// cpu_strobe ________________________________________________________________/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\_______________________________________________________________
// cpu_strobe ________________________________________________________________/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\__________________________________
// cyc ‾‾‾‾\_____________________________________________________________________________________________________________/‾‾‾‾‾‾‾‾‾\____
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// 5.95ns
//
// REFRESH RASCAS
// REFRESH RASCAS RASCAS
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// REFRSH
// REFRSH REFRSH
//
// READ+NOP RAS CAS latch set do
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
@ -128,8 +128,8 @@ always @(posedge clk) begin
// Start - activate (port1) or refresh
25: begin
if (rq1) begin
{SDRAM_BA,SDRAM_A,col} <= Ar1;
if (rq1) begin
sdr_cmd <= SdrCmd_ac;
end
else if (rq2) begin
@ -137,7 +137,6 @@ always @(posedge clk) begin
end
else begin
sdr_cmd <= SdrCmd_re;
state <= 19;
end
end
@ -157,8 +156,8 @@ always @(posedge clk) begin
// Start - activate (port2) or refresh
28: begin
if (rq2) begin
{SDRAM_BA,SDRAM_A,col} <= Ar2;
if (rq2) begin
sdr_cmd <= SdrCmd_ac;
end
end
@ -182,6 +181,10 @@ always @(posedge clk) begin
end
end
if (!rq1 && !rq2) begin
sdr_cmd <= SdrCmd_re;
end
state <= 20;
end