mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
Some cleanup.
This commit is contained in:
sorgelig
52
src/clock.v
52
src/clock.v
@ -12,50 +12,22 @@
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// c2 |________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____| period = 7 duty = 25% phase = 180
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// c3 |____________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>| period = 7 duty = 25% phase = 270
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module clock (
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module clock
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(
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input wire clk,
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input wire [1:0] ay_mod,
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output reg f0, f1,
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output reg h0, h1,
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output reg c0, c1, c2, c3,
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output wire ay_clk,
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output reg ce_saa
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);
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output reg c0, c1, c2, c3
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);
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reg [1:0] cnt;
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always @(posedge clk) begin
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cnt <= cnt + 2'b1;
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reg [1:0] cnt;
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always @(posedge clk)
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begin
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cnt <= cnt + 2'b1;
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{f1, f0} <= 2'b1 << cnt[2'b0];
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{h1, h0} <= 2'b1 << cnt[2'b1];
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{c3, c2, c1, c0} <= 4'b1 << cnt;
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end
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// AY clock generator
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// ay_mod - clock selection for AY, MHz: 00 - 1.75 / 01 - 1.7733 / 10 - 3.5 / 11 - 3.546
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reg [7:0] skip_cnt;
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reg [3:0] ay_cnt;
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assign ay_clk = ay_mod[1] ? ay_cnt[2] : ay_cnt[3];
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always @(posedge clk)
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begin
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skip_cnt <= skip_cnt[7] ? 8'd73 : skip_cnt - 8'd1;
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ay_cnt <= ay_cnt + (skip_cnt[7] & ay_mod[0] ? 4'd2 : 4'd1);
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end
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always @(posedge clk) begin
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reg [2:0] div;
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div <= div + 1'd1;
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if(div == 6) div <= 0;
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ce_saa <= (div == 0 || div == 3);
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end
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{f1, f0} <= 2'b1 << cnt[0];
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{h1, h0} <= 2'b1 << cnt[1];
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{c3, c2, c1, c0} <= 4'b1 << cnt;
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end
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endmodule
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195
src/keyboard.vhd
195
src/keyboard.vhd
@ -17,7 +17,7 @@ port (
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RESET : in std_logic;
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A : in std_logic_vector(7 downto 0);
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KEYB : out std_logic_vector(4 downto 0);
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KEYF : out std_logic_vector(4 downto 0);
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KEY_RESET: out std_logic;
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SCANCODE : out std_logic_vector(7 downto 0);
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PS2_KEY : in std_logic_vector(10 downto 0)
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);
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@ -26,15 +26,9 @@ end keyboard;
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architecture rtl of keyboard is
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-- Internal signals
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type key_matrix is array (11 downto 0) of std_logic_vector(4 downto 0);
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type key_matrix is array (7 downto 0) of std_logic_vector(4 downto 0);
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signal keys : key_matrix;
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signal row0, row1, row2, row3, row4, row5, row6, row7 : std_logic_vector(4 downto 0);
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signal scan : std_logic_vector(7 downto 0);
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-- ps/2 signals
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signal pressrelease_n : std_logic;
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signal pressrelease : std_logic;
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signal flg : std_logic;
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begin
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@ -50,12 +44,6 @@ begin
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row7 <= keys(7) when A(7) = '0' else (others => '1');
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KEYB <= row0 and row1 and row2 and row3 and row4 and row5 and row6 and row7;
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KEYF <= keys(9);
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SCANCODE <= scan;
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pressrelease_n <= not ps2_key(9);
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pressrelease <= ps2_key(9);
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process (CLK) begin
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if rising_edge(CLK) then
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flg <= ps2_key(10);
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@ -69,121 +57,108 @@ begin
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keys(5) <= (others => '1');
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keys(6) <= (others => '1');
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keys(7) <= (others => '1');
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keys(8) <= (others => '0');
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keys(9) <= (others => '0');
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scan <= (others => '0');
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KEY_RESET <= '0';
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SCANCODE <= (others => '0');
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else
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if flg /= ps2_key(10) then
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if (pressrelease = '1') then
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scan <= ps2_key(7 downto 0);
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if (ps2_key(9) = '1') then
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SCANCODE <= ps2_key(7 downto 0);
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else
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scan <= (others => '1');
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SCANCODE <= (others => '1');
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end if;
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case ps2_key(7 downto 0) is
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when X"12" => keys(0)(0) <= pressrelease_n; -- Left shift (CAPS SHIFT)
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when X"59" => keys(0)(0) <= pressrelease_n; -- Right shift (CAPS SHIFT)
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when X"1a" => keys(0)(1) <= pressrelease_n; -- Z
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when X"22" => keys(0)(2) <= pressrelease_n; -- X
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when X"21" => keys(0)(3) <= pressrelease_n; -- C
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when X"2a" => keys(0)(4) <= pressrelease_n; -- V
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when X"12" => keys(0)(0) <= not ps2_key(9); -- Left shift (CAPS SHIFT)
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when X"59" => keys(0)(0) <= not ps2_key(9); -- Right shift (CAPS SHIFT)
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when X"1a" => keys(0)(1) <= not ps2_key(9); -- Z
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when X"22" => keys(0)(2) <= not ps2_key(9); -- X
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when X"21" => keys(0)(3) <= not ps2_key(9); -- C
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when X"2a" => keys(0)(4) <= not ps2_key(9); -- V
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when X"1c" => keys(1)(0) <= pressrelease_n; -- A
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when X"1b" => keys(1)(1) <= pressrelease_n; -- S
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when X"23" => keys(1)(2) <= pressrelease_n; -- D
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when X"2b" => keys(1)(3) <= pressrelease_n; -- F
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when X"34" => keys(1)(4) <= pressrelease_n; -- G
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when X"1c" => keys(1)(0) <= not ps2_key(9); -- A
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when X"1b" => keys(1)(1) <= not ps2_key(9); -- S
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when X"23" => keys(1)(2) <= not ps2_key(9); -- D
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when X"2b" => keys(1)(3) <= not ps2_key(9); -- F
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when X"34" => keys(1)(4) <= not ps2_key(9); -- G
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when X"15" => keys(2)(0) <= pressrelease_n; -- Q
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when X"1d" => keys(2)(1) <= pressrelease_n; -- W
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when X"24" => keys(2)(2) <= pressrelease_n; -- E
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when X"2d" => keys(2)(3) <= pressrelease_n; -- R
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when X"2c" => keys(2)(4) <= pressrelease_n; -- T
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when X"15" => keys(2)(0) <= not ps2_key(9); -- Q
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when X"1d" => keys(2)(1) <= not ps2_key(9); -- W
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when X"24" => keys(2)(2) <= not ps2_key(9); -- E
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when X"2d" => keys(2)(3) <= not ps2_key(9); -- R
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when X"2c" => keys(2)(4) <= not ps2_key(9); -- T
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when X"16" => keys(3)(0) <= pressrelease_n; -- 1
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when X"1e" => keys(3)(1) <= pressrelease_n; -- 2
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when X"26" => keys(3)(2) <= pressrelease_n; -- 3
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when X"25" => keys(3)(3) <= pressrelease_n; -- 4
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when X"2e" => keys(3)(4) <= pressrelease_n; -- 5
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when X"16" => keys(3)(0) <= not ps2_key(9); -- 1
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when X"1e" => keys(3)(1) <= not ps2_key(9); -- 2
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when X"26" => keys(3)(2) <= not ps2_key(9); -- 3
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when X"25" => keys(3)(3) <= not ps2_key(9); -- 4
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when X"2e" => keys(3)(4) <= not ps2_key(9); -- 5
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when X"45" => keys(4)(0) <= pressrelease_n; -- 0
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when X"46" => keys(4)(1) <= pressrelease_n; -- 9
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when X"3e" => keys(4)(2) <= pressrelease_n; -- 8
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when X"3d" => keys(4)(3) <= pressrelease_n; -- 7
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when X"36" => keys(4)(4) <= pressrelease_n; -- 6
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when X"45" => keys(4)(0) <= not ps2_key(9); -- 0
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when X"46" => keys(4)(1) <= not ps2_key(9); -- 9
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when X"3e" => keys(4)(2) <= not ps2_key(9); -- 8
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when X"3d" => keys(4)(3) <= not ps2_key(9); -- 7
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when X"36" => keys(4)(4) <= not ps2_key(9); -- 6
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when X"4d" => keys(5)(0) <= pressrelease_n; -- P
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when X"44" => keys(5)(1) <= pressrelease_n; -- O
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when X"43" => keys(5)(2) <= pressrelease_n; -- I
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when X"3c" => keys(5)(3) <= pressrelease_n; -- U
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when X"35" => keys(5)(4) <= pressrelease_n; -- Y
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when X"4d" => keys(5)(0) <= not ps2_key(9); -- P
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when X"44" => keys(5)(1) <= not ps2_key(9); -- O
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when X"43" => keys(5)(2) <= not ps2_key(9); -- I
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when X"3c" => keys(5)(3) <= not ps2_key(9); -- U
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when X"35" => keys(5)(4) <= not ps2_key(9); -- Y
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when X"5a" => keys(6)(0) <= pressrelease_n; -- ENTER
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when X"4b" => keys(6)(1) <= pressrelease_n; -- L
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when X"42" => keys(6)(2) <= pressrelease_n; -- K
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when X"3b" => keys(6)(3) <= pressrelease_n; -- J
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when X"33" => keys(6)(4) <= pressrelease_n; -- H
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when X"5a" => keys(6)(0) <= not ps2_key(9); -- ENTER
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when X"4b" => keys(6)(1) <= not ps2_key(9); -- L
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when X"42" => keys(6)(2) <= not ps2_key(9); -- K
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when X"3b" => keys(6)(3) <= not ps2_key(9); -- J
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when X"33" => keys(6)(4) <= not ps2_key(9); -- H
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when X"29" => keys(7)(0) <= pressrelease_n; -- SPACE
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--keys(8)(4) <= pressrelease; -- kempston fire
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when X"14" => keys(7)(1) <= pressrelease_n; -- CTRL (Symbol Shift)
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when X"3a" => keys(7)(2) <= pressrelease_n; -- M
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when X"31" => keys(7)(3) <= pressrelease_n; -- N
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when X"32" => keys(7)(4) <= pressrelease_n; -- B
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when X"29" => keys(7)(0) <= not ps2_key(9); -- SPACE
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when X"14" => keys(7)(1) <= not ps2_key(9); -- CTRL (Symbol Shift)
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when X"3a" => keys(7)(2) <= not ps2_key(9); -- M
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when X"31" => keys(7)(3) <= not ps2_key(9); -- N
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when X"32" => keys(7)(4) <= not ps2_key(9); -- B
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-- Cursor keys
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when X"6b" => keys(0)(0) <= pressrelease_n; -- Left (CAPS 5)
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keys(3)(4) <= pressrelease_n;
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--keys(8)(1) <= pressrelease; -- kempston left
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when X"72" => keys(0)(0) <= pressrelease_n; -- Down (CAPS 6)
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keys(4)(4) <= pressrelease_n;
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--keys(8)(2) <= pressrelease; -- kempston down
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when X"75" => keys(0)(0) <= pressrelease_n; -- Up (CAPS 7)
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keys(4)(3) <= pressrelease_n;
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--keys(8)(3) <= pressrelease; -- kempston up
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when X"74" => keys(0)(0) <= pressrelease_n; -- Right (CAPS 8)
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keys(4)(2) <= pressrelease_n;
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--keys(8)(0) <= pressrelease; -- kempston right
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when X"6b" => keys(0)(0) <= not ps2_key(9); -- Left (CAPS 5)
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keys(3)(4) <= not ps2_key(9);
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when X"72" => keys(0)(0) <= not ps2_key(9); -- Down (CAPS 6)
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keys(4)(4) <= not ps2_key(9);
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when X"75" => keys(0)(0) <= not ps2_key(9); -- Up (CAPS 7)
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keys(4)(3) <= not ps2_key(9);
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when X"74" => keys(0)(0) <= not ps2_key(9); -- Right (CAPS 8)
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keys(4)(2) <= not ps2_key(9);
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-- Other special keys sent to the ULA as key combinations
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when X"66" => keys(0)(0) <= pressrelease_n; -- Backspace (CAPS 0)
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keys(4)(0) <= pressrelease_n;
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when X"58" => keys(0)(0) <= pressrelease_n; -- Caps lock (CAPS 2)
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keys(3)(1) <= pressrelease_n;
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when X"0d" => keys(0)(0) <= pressrelease_n; -- Tab (CAPS SPACE)
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keys(7)(0) <= pressrelease_n;
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when X"49" => keys(7)(2) <= pressrelease_n; -- .
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keys(7)(1) <= pressrelease_n;
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when X"4e" => keys(6)(3) <= pressrelease_n; -- -
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keys(7)(1) <= pressrelease_n;
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when X"0e" => keys(3)(0) <= pressrelease_n; -- ` (EDIT)
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keys(0)(0) <= pressrelease_n;
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when X"41" => keys(7)(3) <= pressrelease_n; -- ,
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keys(7)(1) <= pressrelease_n;
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when X"4c" => keys(5)(1) <= pressrelease_n; -- ;
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keys(7)(1) <= pressrelease_n;
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when X"52" => keys(5)(0) <= pressrelease_n; -- "
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keys(7)(1) <= pressrelease_n;
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when X"5d" => keys(0)(1) <= pressrelease_n; -- :
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keys(7)(1) <= pressrelease_n;
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when X"55" => keys(6)(1) <= pressrelease_n; -- =
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keys(7)(1) <= pressrelease_n;
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when X"54" => keys(4)(2) <= pressrelease_n; -- (
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keys(7)(1) <= pressrelease_n;
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when X"5b" => keys(4)(1) <= pressrelease_n; -- )
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keys(7)(1) <= pressrelease_n;
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when X"4a" => keys(0)(3) <= pressrelease_n; -- ?
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keys(7)(1) <= pressrelease_n;
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when X"66" => keys(0)(0) <= not ps2_key(9); -- Backspace (CAPS 0)
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keys(4)(0) <= not ps2_key(9);
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when X"58" => keys(0)(0) <= not ps2_key(9); -- Caps lock (CAPS 2)
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keys(3)(1) <= not ps2_key(9);
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when X"0d" => keys(0)(0) <= not ps2_key(9); -- Tab (CAPS SPACE)
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keys(7)(0) <= not ps2_key(9);
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when X"49" => keys(7)(2) <= not ps2_key(9); -- .
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keys(7)(1) <= not ps2_key(9);
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when X"4e" => keys(6)(3) <= not ps2_key(9); -- -
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keys(7)(1) <= not ps2_key(9);
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when X"0e" => keys(3)(0) <= not ps2_key(9); -- ` (EDIT)
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keys(0)(0) <= not ps2_key(9);
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when X"41" => keys(7)(3) <= not ps2_key(9); -- ,
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keys(7)(1) <= not ps2_key(9);
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when X"4c" => keys(5)(1) <= not ps2_key(9); -- ;
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keys(7)(1) <= not ps2_key(9);
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when X"52" => keys(5)(0) <= not ps2_key(9); -- "
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keys(7)(1) <= not ps2_key(9);
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when X"5d" => keys(0)(1) <= not ps2_key(9); -- :
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keys(7)(1) <= not ps2_key(9);
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when X"55" => keys(6)(1) <= not ps2_key(9); -- =
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keys(7)(1) <= not ps2_key(9);
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when X"54" => keys(4)(2) <= not ps2_key(9); -- (
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keys(7)(1) <= not ps2_key(9);
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when X"5b" => keys(4)(1) <= not ps2_key(9); -- )
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keys(7)(1) <= not ps2_key(9);
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when X"4a" => keys(0)(3) <= not ps2_key(9); -- ?
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keys(7)(1) <= not ps2_key(9);
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--------------------------------------------
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-- Soft keys
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when X"78" => keys(9)(1) <= pressrelease; -- F11
|
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when X"07" => keys(9)(0) <= pressrelease; -- F12
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-- Hardware keys
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when X"7c" => keys(9)(2) <= pressrelease; -- PrtScr
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when X"7e" => keys(9)(3) <= pressrelease; -- Scroll Lock
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when X"48" => keys(9)(4) <= pressrelease; -- Pause
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when X"78" => KEY_RESET <= ps2_key(9); -- F11
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when others => null;
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end case;
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163
src/spi.v
163
src/spi.v
@ -57,136 +57,91 @@
|
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// to the known state from any operational state, set speed=0 and start=1 for 8 clks
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// (that starts Fclk/Fspi=2 speed transfer for sure), then remain start=0, speed=0 for at least 18 clks.
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//`include "../include/tune.v"
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|
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module spi(
|
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module spi
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(
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// SPI wires
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||||
input wire clk, // system clk
|
||||
output wire sck, // SPI bus pins...
|
||||
output wire sdo, //
|
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input wire sdi, //
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input wire sdi, //
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||||
|
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// controls
|
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output wire stb, // ready strobe, 1 clock length
|
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output wire start, // start strobe, 1 clock length
|
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// output wire rdy, // ready (idle) - when module can accept data
|
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output reg bsync, // for vs1001
|
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output reg bsync, // for vs1001
|
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|
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// DMA interface
|
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input wire dma_req,
|
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input wire [7:0] dma_din,
|
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input wire [7:0] dma_din,
|
||||
|
||||
// Z80 interface
|
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input wire cpu_req,
|
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input wire [7:0] cpu_din,
|
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output reg [7:0] dout,
|
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output reg [7:0] dout,
|
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|
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// configuration
|
||||
input wire [1:0] speed, // =2'b00 - sck full speed (1/2 of clk), =2'b01 - half (1/4 of clk), =2'b10 - one fourth (1/8 of clk), =2'b11 - one eighth (1/16 of clk)
|
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output reg [2:0] tst
|
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input wire [1:0] speed // =0 - sck full speed (1/2 of clk), =1 - half (1/4 of clk), =2 - one fourth (1/8 of clk), =3 - one eighth (1/16 of clk)
|
||||
);
|
||||
|
||||
always @*
|
||||
if (stb)
|
||||
tst = 5;
|
||||
else if (start)
|
||||
tst = 3;
|
||||
else if (dma_req)
|
||||
tst = 1;
|
||||
else if (cpu_req)
|
||||
tst = 4;
|
||||
else tst = 0;
|
||||
|
||||
wire req = cpu_req || dma_req;
|
||||
wire [7:0] din = dma_req ? dma_din : cpu_din;
|
||||
wire req = cpu_req || dma_req;
|
||||
wire [7:0] din = dma_req ? dma_din : cpu_din;
|
||||
|
||||
//initial // for simulation only!
|
||||
//begin
|
||||
// counter = 5'b10000;
|
||||
// shiftout = 8'd0;
|
||||
// shiftout = 7'd0;
|
||||
// bsync = 1'd0;
|
||||
// dout = 1'b0;
|
||||
//end
|
||||
// sdo is high bit of shiftout
|
||||
assign sdo = shiftout[7];
|
||||
wire ena_shout_load = (start || sck) & g_ena; // enable load of shiftout register
|
||||
assign sck = counter[0];
|
||||
wire rdy = counter[4]; // =0 when transmission in progress
|
||||
assign stb = stb_r && !rdy;
|
||||
assign start = req && rdy;
|
||||
|
||||
// sdo is high bit of shiftout
|
||||
assign sdo = shiftout[7];
|
||||
wire ena_shout_load = (start || sck) & g_ena; // enable load of shiftout register
|
||||
assign sck = counter[0];
|
||||
wire rdy = counter[4]; // =0 when transmission in progress
|
||||
assign stb = stb_r && !rdy;
|
||||
assign start = req && rdy;
|
||||
|
||||
reg [6:0] shiftin; // shifting in data from sdi before emitting it on dout
|
||||
reg [4:0] counter; // handles transmission
|
||||
reg stb_r;
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (g_ena)
|
||||
begin
|
||||
if (start)
|
||||
begin
|
||||
counter <= 5'b0; // rdy = 0; sck = 0;
|
||||
bsync <= 1'b1; // begin bsync pulse
|
||||
stb_r <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (!sck) // on the rising edge of sck
|
||||
begin
|
||||
shiftin[6:0] <= {shiftin[5:0], sdi};
|
||||
if (&counter[3:1] && !rdy)
|
||||
begin
|
||||
dout <= {shiftin[6:0], sdi}; // update dout at the last sck rising edge
|
||||
stb_r <= 1'b1;
|
||||
end
|
||||
reg [6:0] shiftin; // shifting in data from sdi before emitting it on dout
|
||||
reg [4:0] counter; // handles transmission
|
||||
reg stb_r;
|
||||
always @(posedge clk) begin
|
||||
if (g_ena) begin
|
||||
if (start) begin
|
||||
counter <= 5'b0; // rdy = 0; sck = 0;
|
||||
bsync <= 1'b1; // begin bsync pulse
|
||||
stb_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (!sck) begin // on the rising edge of sck
|
||||
shiftin[6:0] <= {shiftin[5:0], sdi};
|
||||
if (&counter[3:1] && !rdy) begin
|
||||
dout <= {shiftin[6:0], sdi}; // update dout at the last sck rising edge
|
||||
stb_r <= 1'b1;
|
||||
end
|
||||
else // on the falling edge of sck
|
||||
begin
|
||||
bsync <= 1'b0;
|
||||
end
|
||||
if (!rdy)
|
||||
counter <= counter + 5'd1;
|
||||
end
|
||||
else begin // on the falling edge of sck
|
||||
bsync <= 1'b0;
|
||||
end
|
||||
if (!rdy) counter <= counter + 5'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// shiftout treatment is done so just to save LCELLs in acex1k
|
||||
reg [7:0] shiftout; // shifting out data to the sdo
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (ena_shout_load)
|
||||
begin
|
||||
if (start)
|
||||
shiftout <= din;
|
||||
else // sck
|
||||
shiftout[7:0] <= {shiftout[6:0], shiftout[0]}; // last bit remains after end of exchange
|
||||
end
|
||||
// shiftout treatment is done so just to save LCELLs in acex1k
|
||||
reg [7:0] shiftout; // shifting out data to the sdo
|
||||
always @(posedge clk) begin
|
||||
if (ena_shout_load) begin
|
||||
if (start) shiftout <= din;
|
||||
else shiftout[7:0] <= {shiftout[6:0], shiftout[0]}; // last bit remains after end of exchange
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// slow speeds - controlled by g_ena
|
||||
reg [2:0] wcnt;
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (|speed)
|
||||
begin
|
||||
if (start)
|
||||
wcnt <= 3'b001;
|
||||
else if (rdy)
|
||||
wcnt <= 3'b000;
|
||||
else
|
||||
wcnt <= wcnt + 3'd1;
|
||||
end
|
||||
else
|
||||
wcnt <= 3'b000;
|
||||
// slow speeds - controlled by g_ena
|
||||
reg [2:0] wcnt;
|
||||
always @(posedge clk) begin
|
||||
if (|speed) begin
|
||||
if (start) wcnt <= 1;
|
||||
else if (rdy) wcnt <= 0;
|
||||
else wcnt <= wcnt + 1'd1;
|
||||
end
|
||||
else wcnt <= 0;
|
||||
end
|
||||
|
||||
|
||||
wire g_ena = g_en[speed];
|
||||
wire g_en[0:3];
|
||||
assign g_en[0] = 1'b1;
|
||||
assign g_en[1] = ~|wcnt[0];
|
||||
assign g_en[2] = ~|wcnt[1:0];
|
||||
assign g_en[3] = ~|wcnt[2:0];
|
||||
|
||||
wire [3:0] g_en = {~|wcnt[2:0], ~|wcnt[1:0], ~|wcnt[0], 1'b1};
|
||||
wire g_ena = g_en[speed];
|
||||
|
||||
endmodule
|
||||
|
||||
54
src/tsconf.v
54
src/tsconf.v
@ -296,7 +296,6 @@ wire [7:0] mouse_do;
|
||||
clock TS01
|
||||
(
|
||||
.clk(clk_28mhz),
|
||||
.ay_mod(0),
|
||||
.f0(f0),
|
||||
.f1(f1),
|
||||
.h0(h0),
|
||||
@ -304,8 +303,7 @@ clock TS01
|
||||
.c0(c0),
|
||||
.c1(c1),
|
||||
.c2(c2),
|
||||
.c3(c3),
|
||||
.ce_saa(ce_saa)
|
||||
.c3(c3)
|
||||
);
|
||||
|
||||
zclock TS02
|
||||
@ -330,11 +328,11 @@ T80s #(.mode(0), .t2write(1), .iowait(1)) z80_unit
|
||||
(
|
||||
.reset_n((~reset)),
|
||||
.clk_n(zclk),
|
||||
.cen(1'b1),
|
||||
.wait_n(1'b1),
|
||||
.cen(1),
|
||||
.wait_n(1),
|
||||
.int_n(cpu_int_n_TS),
|
||||
.nmi_n(1'b1),
|
||||
.busrq_n(1'b1),
|
||||
.nmi_n(1),
|
||||
.busrq_n(1),
|
||||
.m1_n(cpu_m1_n),
|
||||
.mreq_n(cpu_mreq_n),
|
||||
.iorq_n(cpu_iorq_n),
|
||||
@ -438,12 +436,12 @@ zports TS05
|
||||
.vdos_on(vdos_on),
|
||||
.vdos_off(vdos_off),
|
||||
.rstrom(2'b11),
|
||||
.tape_read(1'b1),
|
||||
.tape_read(1),
|
||||
.keys_in(kb_do_bus), // keys (port FE)
|
||||
.mus_in(mouse_do), // mouse (xxDF)
|
||||
.kj_in(joystick),
|
||||
.vg_intrq(1'b0),
|
||||
.vg_drq(1'b0), // from vg93 module - drq + irq read
|
||||
.vg_intrq(0),
|
||||
.vg_drq(0), // from vg93 module - drq + irq read
|
||||
.sdcs_n(SD_CS_N), // to SD card
|
||||
.sd_start(cpu_spi_req), // to SPI
|
||||
.sd_datain(cpu_spi_din), // to SPI(7 downto 0);
|
||||
@ -453,7 +451,7 @@ zports TS05
|
||||
.com_data_rx(8'b00000000), //uart_do_bus,
|
||||
.com_status(8'b10010000), //'1' & uart_tx_empty & uart_tx_fifo_empty & "1000" & uart_rx_avail,
|
||||
//com_status=> '0' & uart_tx_empty & uart_tx_fifo_empty & "0000" & '1',
|
||||
.lock_conf(1'b1)
|
||||
.lock_conf(1)
|
||||
);
|
||||
|
||||
zmem TS06
|
||||
@ -495,8 +493,8 @@ zmem TS06
|
||||
.cpu_latch(cpu_latch),
|
||||
.cpu_stall(cpu_stall), // for Zclock if HI-> STALL (ZCLK)
|
||||
.loader(0), // ROM for loader active
|
||||
.testkey(1'b1),
|
||||
.intt(1'b0)
|
||||
.testkey(1),
|
||||
.intt(0)
|
||||
);
|
||||
|
||||
arbiter TS07
|
||||
@ -665,8 +663,7 @@ zmaps TS10
|
||||
.cram_we(cram_we),
|
||||
.sfile_we(sfile_we)
|
||||
);
|
||||
|
||||
|
||||
|
||||
spi TS11
|
||||
(
|
||||
.clk(clk_28mhz),
|
||||
@ -680,7 +677,7 @@ spi TS11
|
||||
.cpu_req(cpu_spi_req),
|
||||
.cpu_din(cpu_spi_din),
|
||||
.dout(spi_dout),
|
||||
.speed(2'b00)
|
||||
.speed(0)
|
||||
);
|
||||
|
||||
zint TS13
|
||||
@ -738,7 +735,7 @@ sdram SE4
|
||||
|
||||
// PS/2 Keyboard
|
||||
wire [4:0] kb_do_bus;
|
||||
wire [4:0] kb_f_bus;
|
||||
wire key_reset;
|
||||
wire [7:0] key_scancode;
|
||||
|
||||
keyboard SE5
|
||||
@ -747,7 +744,7 @@ keyboard SE5
|
||||
.reset(COLD_RESET | WARM_RESET),
|
||||
.a(cpu_a_bus[15:8]),
|
||||
.keyb(kb_do_bus),
|
||||
.keyf(kb_f_bus),
|
||||
.KEY_RESET(key_reset),
|
||||
.scancode(key_scancode),
|
||||
.ps2_key(PS2_KEY)
|
||||
);
|
||||
@ -784,7 +781,7 @@ mc146818a SE9
|
||||
.reset(reset),
|
||||
.clk(clk_28mhz),
|
||||
.ena(ena_0_4375mhz),
|
||||
.cs(1'b1),
|
||||
.cs(1),
|
||||
.keyscancode(key_scancode),
|
||||
.rtc(RTC),
|
||||
.cmoscfg(CMOSCfg),
|
||||
@ -805,7 +802,7 @@ soundrive SE10
|
||||
(
|
||||
.reset(reset),
|
||||
.clk(clk_28mhz),
|
||||
.cs(1'b1),
|
||||
.cs(1),
|
||||
.wr_n(cpu_wr_n),
|
||||
.a(cpu_a_bus[7:0]),
|
||||
.di(cpu_do_bus),
|
||||
@ -891,15 +888,24 @@ gs #("src/sound/gs105b.mif") U15
|
||||
// SAA1099
|
||||
wire [7:0] saa_out_l;
|
||||
wire [7:0] saa_out_r;
|
||||
wire ce_saa;
|
||||
wire saa_wr_n = ~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFF && ~dos;
|
||||
|
||||
reg ce_saa;
|
||||
always @(posedge clk_28mhz) begin
|
||||
reg [2:0] div;
|
||||
|
||||
div <= div + 1'd1;
|
||||
if(div == 6) div <= 0;
|
||||
|
||||
ce_saa <= (div == 0 || div == 3);
|
||||
end
|
||||
|
||||
saa1099 U16
|
||||
(
|
||||
.clk_sys(clk_28mhz),
|
||||
.ce(ce_saa),
|
||||
.rst_n((~reset)),
|
||||
.cs_n(1'b0),
|
||||
.rst_n(~reset),
|
||||
.cs_n(0),
|
||||
.a0(cpu_a_bus[8]), // 0=data, 1=address
|
||||
.wr_n(saa_wr_n),
|
||||
.din(cpu_do_bus),
|
||||
@ -921,7 +927,7 @@ compressor compressor
|
||||
//-----------------------------------------------------------------------------
|
||||
// Global
|
||||
//-----------------------------------------------------------------------------
|
||||
wire reset = COLD_RESET | WARM_RESET | kb_f_bus[1]; // Reset
|
||||
wire reset = COLD_RESET | WARM_RESET | key_reset;
|
||||
assign RESET_OUT = reset;
|
||||
|
||||
// CPU interface
|
||||
|
||||
Reference in New Issue
Block a user