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Some cleanup.

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sorgelig
2018-08-20 18:59:20 +08:00
parent 6502164af1
commit 7d7901932f
4 changed files with 186 additions and 278 deletions
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52
src/clock.v
View File

@ -12,50 +12,22 @@
// c2 |________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____| period = 7 duty = 25% phase = 180 // c2 |________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>____| period = 7 duty = 25% phase = 180
// c3 |____________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>| period = 7 duty = 25% phase = 270 // c3 |____________<EFBFBD><EFBFBD><EFBFBD><EFBFBD>| period = 7 duty = 25% phase = 270
module clock ( module clock
(
input wire clk, input wire clk,
input wire [1:0] ay_mod,
output reg f0, f1, output reg f0, f1,
output reg h0, h1, output reg h0, h1,
output reg c0, c1, c2, c3, output reg c0, c1, c2, c3
output wire ay_clk, );
output reg ce_saa
);
reg [1:0] cnt;
always @(posedge clk) begin
cnt <= cnt + 2'b1;
reg [1:0] cnt; {f1, f0} <= 2'b1 << cnt[0];
{h1, h0} <= 2'b1 << cnt[1];
always @(posedge clk) {c3, c2, c1, c0} <= 4'b1 << cnt;
begin end
cnt <= cnt + 2'b1;
{f1, f0} <= 2'b1 << cnt[2'b0];
{h1, h0} <= 2'b1 << cnt[2'b1];
{c3, c2, c1, c0} <= 4'b1 << cnt;
end
// AY clock generator
// ay_mod - clock selection for AY, MHz: 00 - 1.75 / 01 - 1.7733 / 10 - 3.5 / 11 - 3.546
reg [7:0] skip_cnt;
reg [3:0] ay_cnt;
assign ay_clk = ay_mod[1] ? ay_cnt[2] : ay_cnt[3];
always @(posedge clk)
begin
skip_cnt <= skip_cnt[7] ? 8'd73 : skip_cnt - 8'd1;
ay_cnt <= ay_cnt + (skip_cnt[7] & ay_mod[0] ? 4'd2 : 4'd1);
end
always @(posedge clk) begin
reg [2:0] div;
div <= div + 1'd1;
if(div == 6) div <= 0;
ce_saa <= (div == 0 || div == 3);
end
endmodule endmodule

195
src/keyboard.vhd
View File

@ -17,7 +17,7 @@ port (
RESET : in std_logic; RESET : in std_logic;
A : in std_logic_vector(7 downto 0); A : in std_logic_vector(7 downto 0);
KEYB : out std_logic_vector(4 downto 0); KEYB : out std_logic_vector(4 downto 0);
KEYF : out std_logic_vector(4 downto 0); KEY_RESET: out std_logic;
SCANCODE : out std_logic_vector(7 downto 0); SCANCODE : out std_logic_vector(7 downto 0);
PS2_KEY : in std_logic_vector(10 downto 0) PS2_KEY : in std_logic_vector(10 downto 0)
); );
@ -26,15 +26,9 @@ end keyboard;
architecture rtl of keyboard is architecture rtl of keyboard is
-- Internal signals -- Internal signals
type key_matrix is array (11 downto 0) of std_logic_vector(4 downto 0); type key_matrix is array (7 downto 0) of std_logic_vector(4 downto 0);
signal keys : key_matrix; signal keys : key_matrix;
signal row0, row1, row2, row3, row4, row5, row6, row7 : std_logic_vector(4 downto 0); signal row0, row1, row2, row3, row4, row5, row6, row7 : std_logic_vector(4 downto 0);
signal scan : std_logic_vector(7 downto 0);
-- ps/2 signals
signal pressrelease_n : std_logic;
signal pressrelease : std_logic;
signal flg : std_logic; signal flg : std_logic;
begin begin
@ -50,12 +44,6 @@ begin
row7 <= keys(7) when A(7) = '0' else (others => '1'); row7 <= keys(7) when A(7) = '0' else (others => '1');
KEYB <= row0 and row1 and row2 and row3 and row4 and row5 and row6 and row7; KEYB <= row0 and row1 and row2 and row3 and row4 and row5 and row6 and row7;
KEYF <= keys(9);
SCANCODE <= scan;
pressrelease_n <= not ps2_key(9);
pressrelease <= ps2_key(9);
process (CLK) begin process (CLK) begin
if rising_edge(CLK) then if rising_edge(CLK) then
flg <= ps2_key(10); flg <= ps2_key(10);
@ -69,121 +57,108 @@ begin
keys(5) <= (others => '1'); keys(5) <= (others => '1');
keys(6) <= (others => '1'); keys(6) <= (others => '1');
keys(7) <= (others => '1'); keys(7) <= (others => '1');
keys(8) <= (others => '0'); KEY_RESET <= '0';
keys(9) <= (others => '0'); SCANCODE <= (others => '0');
scan <= (others => '0');
else else
if flg /= ps2_key(10) then if flg /= ps2_key(10) then
if (pressrelease = '1') then if (ps2_key(9) = '1') then
scan <= ps2_key(7 downto 0); SCANCODE <= ps2_key(7 downto 0);
else else
scan <= (others => '1'); SCANCODE <= (others => '1');
end if; end if;
case ps2_key(7 downto 0) is case ps2_key(7 downto 0) is
when X"12" => keys(0)(0) <= pressrelease_n; -- Left shift (CAPS SHIFT) when X"12" => keys(0)(0) <= not ps2_key(9); -- Left shift (CAPS SHIFT)
when X"59" => keys(0)(0) <= pressrelease_n; -- Right shift (CAPS SHIFT) when X"59" => keys(0)(0) <= not ps2_key(9); -- Right shift (CAPS SHIFT)
when X"1a" => keys(0)(1) <= pressrelease_n; -- Z when X"1a" => keys(0)(1) <= not ps2_key(9); -- Z
when X"22" => keys(0)(2) <= pressrelease_n; -- X when X"22" => keys(0)(2) <= not ps2_key(9); -- X
when X"21" => keys(0)(3) <= pressrelease_n; -- C when X"21" => keys(0)(3) <= not ps2_key(9); -- C
when X"2a" => keys(0)(4) <= pressrelease_n; -- V when X"2a" => keys(0)(4) <= not ps2_key(9); -- V
when X"1c" => keys(1)(0) <= pressrelease_n; -- A when X"1c" => keys(1)(0) <= not ps2_key(9); -- A
when X"1b" => keys(1)(1) <= pressrelease_n; -- S when X"1b" => keys(1)(1) <= not ps2_key(9); -- S
when X"23" => keys(1)(2) <= pressrelease_n; -- D when X"23" => keys(1)(2) <= not ps2_key(9); -- D
when X"2b" => keys(1)(3) <= pressrelease_n; -- F when X"2b" => keys(1)(3) <= not ps2_key(9); -- F
when X"34" => keys(1)(4) <= pressrelease_n; -- G when X"34" => keys(1)(4) <= not ps2_key(9); -- G
when X"15" => keys(2)(0) <= pressrelease_n; -- Q when X"15" => keys(2)(0) <= not ps2_key(9); -- Q
when X"1d" => keys(2)(1) <= pressrelease_n; -- W when X"1d" => keys(2)(1) <= not ps2_key(9); -- W
when X"24" => keys(2)(2) <= pressrelease_n; -- E when X"24" => keys(2)(2) <= not ps2_key(9); -- E
when X"2d" => keys(2)(3) <= pressrelease_n; -- R when X"2d" => keys(2)(3) <= not ps2_key(9); -- R
when X"2c" => keys(2)(4) <= pressrelease_n; -- T when X"2c" => keys(2)(4) <= not ps2_key(9); -- T
when X"16" => keys(3)(0) <= pressrelease_n; -- 1 when X"16" => keys(3)(0) <= not ps2_key(9); -- 1
when X"1e" => keys(3)(1) <= pressrelease_n; -- 2 when X"1e" => keys(3)(1) <= not ps2_key(9); -- 2
when X"26" => keys(3)(2) <= pressrelease_n; -- 3 when X"26" => keys(3)(2) <= not ps2_key(9); -- 3
when X"25" => keys(3)(3) <= pressrelease_n; -- 4 when X"25" => keys(3)(3) <= not ps2_key(9); -- 4
when X"2e" => keys(3)(4) <= pressrelease_n; -- 5 when X"2e" => keys(3)(4) <= not ps2_key(9); -- 5
when X"45" => keys(4)(0) <= pressrelease_n; -- 0 when X"45" => keys(4)(0) <= not ps2_key(9); -- 0
when X"46" => keys(4)(1) <= pressrelease_n; -- 9 when X"46" => keys(4)(1) <= not ps2_key(9); -- 9
when X"3e" => keys(4)(2) <= pressrelease_n; -- 8 when X"3e" => keys(4)(2) <= not ps2_key(9); -- 8
when X"3d" => keys(4)(3) <= pressrelease_n; -- 7 when X"3d" => keys(4)(3) <= not ps2_key(9); -- 7
when X"36" => keys(4)(4) <= pressrelease_n; -- 6 when X"36" => keys(4)(4) <= not ps2_key(9); -- 6
when X"4d" => keys(5)(0) <= pressrelease_n; -- P when X"4d" => keys(5)(0) <= not ps2_key(9); -- P
when X"44" => keys(5)(1) <= pressrelease_n; -- O when X"44" => keys(5)(1) <= not ps2_key(9); -- O
when X"43" => keys(5)(2) <= pressrelease_n; -- I when X"43" => keys(5)(2) <= not ps2_key(9); -- I
when X"3c" => keys(5)(3) <= pressrelease_n; -- U when X"3c" => keys(5)(3) <= not ps2_key(9); -- U
when X"35" => keys(5)(4) <= pressrelease_n; -- Y when X"35" => keys(5)(4) <= not ps2_key(9); -- Y
when X"5a" => keys(6)(0) <= pressrelease_n; -- ENTER when X"5a" => keys(6)(0) <= not ps2_key(9); -- ENTER
when X"4b" => keys(6)(1) <= pressrelease_n; -- L when X"4b" => keys(6)(1) <= not ps2_key(9); -- L
when X"42" => keys(6)(2) <= pressrelease_n; -- K when X"42" => keys(6)(2) <= not ps2_key(9); -- K
when X"3b" => keys(6)(3) <= pressrelease_n; -- J when X"3b" => keys(6)(3) <= not ps2_key(9); -- J
when X"33" => keys(6)(4) <= pressrelease_n; -- H when X"33" => keys(6)(4) <= not ps2_key(9); -- H
when X"29" => keys(7)(0) <= pressrelease_n; -- SPACE when X"29" => keys(7)(0) <= not ps2_key(9); -- SPACE
--keys(8)(4) <= pressrelease; -- kempston fire when X"14" => keys(7)(1) <= not ps2_key(9); -- CTRL (Symbol Shift)
when X"14" => keys(7)(1) <= pressrelease_n; -- CTRL (Symbol Shift) when X"3a" => keys(7)(2) <= not ps2_key(9); -- M
when X"3a" => keys(7)(2) <= pressrelease_n; -- M when X"31" => keys(7)(3) <= not ps2_key(9); -- N
when X"31" => keys(7)(3) <= pressrelease_n; -- N when X"32" => keys(7)(4) <= not ps2_key(9); -- B
when X"32" => keys(7)(4) <= pressrelease_n; -- B
-- Cursor keys -- Cursor keys
when X"6b" => keys(0)(0) <= pressrelease_n; -- Left (CAPS 5) when X"6b" => keys(0)(0) <= not ps2_key(9); -- Left (CAPS 5)
keys(3)(4) <= pressrelease_n; keys(3)(4) <= not ps2_key(9);
--keys(8)(1) <= pressrelease; -- kempston left when X"72" => keys(0)(0) <= not ps2_key(9); -- Down (CAPS 6)
when X"72" => keys(0)(0) <= pressrelease_n; -- Down (CAPS 6) keys(4)(4) <= not ps2_key(9);
keys(4)(4) <= pressrelease_n; when X"75" => keys(0)(0) <= not ps2_key(9); -- Up (CAPS 7)
--keys(8)(2) <= pressrelease; -- kempston down keys(4)(3) <= not ps2_key(9);
when X"75" => keys(0)(0) <= pressrelease_n; -- Up (CAPS 7) when X"74" => keys(0)(0) <= not ps2_key(9); -- Right (CAPS 8)
keys(4)(3) <= pressrelease_n; keys(4)(2) <= not ps2_key(9);
--keys(8)(3) <= pressrelease; -- kempston up
when X"74" => keys(0)(0) <= pressrelease_n; -- Right (CAPS 8)
keys(4)(2) <= pressrelease_n;
--keys(8)(0) <= pressrelease; -- kempston right
-- Other special keys sent to the ULA as key combinations -- Other special keys sent to the ULA as key combinations
when X"66" => keys(0)(0) <= pressrelease_n; -- Backspace (CAPS 0) when X"66" => keys(0)(0) <= not ps2_key(9); -- Backspace (CAPS 0)
keys(4)(0) <= pressrelease_n; keys(4)(0) <= not ps2_key(9);
when X"58" => keys(0)(0) <= pressrelease_n; -- Caps lock (CAPS 2) when X"58" => keys(0)(0) <= not ps2_key(9); -- Caps lock (CAPS 2)
keys(3)(1) <= pressrelease_n; keys(3)(1) <= not ps2_key(9);
when X"0d" => keys(0)(0) <= pressrelease_n; -- Tab (CAPS SPACE) when X"0d" => keys(0)(0) <= not ps2_key(9); -- Tab (CAPS SPACE)
keys(7)(0) <= pressrelease_n; keys(7)(0) <= not ps2_key(9);
when X"49" => keys(7)(2) <= pressrelease_n; -- . when X"49" => keys(7)(2) <= not ps2_key(9); -- .
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"4e" => keys(6)(3) <= pressrelease_n; -- - when X"4e" => keys(6)(3) <= not ps2_key(9); -- -
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"0e" => keys(3)(0) <= pressrelease_n; -- ` (EDIT) when X"0e" => keys(3)(0) <= not ps2_key(9); -- ` (EDIT)
keys(0)(0) <= pressrelease_n; keys(0)(0) <= not ps2_key(9);
when X"41" => keys(7)(3) <= pressrelease_n; -- , when X"41" => keys(7)(3) <= not ps2_key(9); -- ,
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"4c" => keys(5)(1) <= pressrelease_n; -- ; when X"4c" => keys(5)(1) <= not ps2_key(9); -- ;
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"52" => keys(5)(0) <= pressrelease_n; -- " when X"52" => keys(5)(0) <= not ps2_key(9); -- "
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"5d" => keys(0)(1) <= pressrelease_n; -- : when X"5d" => keys(0)(1) <= not ps2_key(9); -- :
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"55" => keys(6)(1) <= pressrelease_n; -- = when X"55" => keys(6)(1) <= not ps2_key(9); -- =
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"54" => keys(4)(2) <= pressrelease_n; -- ( when X"54" => keys(4)(2) <= not ps2_key(9); -- (
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"5b" => keys(4)(1) <= pressrelease_n; -- ) when X"5b" => keys(4)(1) <= not ps2_key(9); -- )
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
when X"4a" => keys(0)(3) <= pressrelease_n; -- ? when X"4a" => keys(0)(3) <= not ps2_key(9); -- ?
keys(7)(1) <= pressrelease_n; keys(7)(1) <= not ps2_key(9);
-------------------------------------------- --------------------------------------------
-- Soft keys when X"78" => KEY_RESET <= ps2_key(9); -- F11
when X"78" => keys(9)(1) <= pressrelease; -- F11
when X"07" => keys(9)(0) <= pressrelease; -- F12
-- Hardware keys
when X"7c" => keys(9)(2) <= pressrelease; -- PrtScr
when X"7e" => keys(9)(3) <= pressrelease; -- Scroll Lock
when X"48" => keys(9)(4) <= pressrelease; -- Pause
when others => null; when others => null;
end case; end case;

163
src/spi.v
View File

@ -57,136 +57,91 @@
// to the known state from any operational state, set speed=0 and start=1 for 8 clks // to the known state from any operational state, set speed=0 and start=1 for 8 clks
// (that starts Fclk/Fspi=2 speed transfer for sure), then remain start=0, speed=0 for at least 18 clks. // (that starts Fclk/Fspi=2 speed transfer for sure), then remain start=0, speed=0 for at least 18 clks.
//`include "../include/tune.v" module spi
(
module spi(
// SPI wires // SPI wires
input wire clk, // system clk input wire clk, // system clk
output wire sck, // SPI bus pins... output wire sck, // SPI bus pins...
output wire sdo, // output wire sdo, //
input wire sdi, // input wire sdi, //
// controls // controls
output wire stb, // ready strobe, 1 clock length output wire stb, // ready strobe, 1 clock length
output wire start, // start strobe, 1 clock length output wire start, // start strobe, 1 clock length
// output wire rdy, // ready (idle) - when module can accept data output reg bsync, // for vs1001
output reg bsync, // for vs1001
// DMA interface // DMA interface
input wire dma_req, input wire dma_req,
input wire [7:0] dma_din, input wire [7:0] dma_din,
// Z80 interface // Z80 interface
input wire cpu_req, input wire cpu_req,
input wire [7:0] cpu_din, input wire [7:0] cpu_din,
output reg [7:0] dout, output reg [7:0] dout,
// configuration // configuration
input wire [1:0] speed, // =2'b00 - sck full speed (1/2 of clk), =2'b01 - half (1/4 of clk), =2'b10 - one fourth (1/8 of clk), =2'b11 - one eighth (1/16 of clk) input wire [1:0] speed // =0 - sck full speed (1/2 of clk), =1 - half (1/4 of clk), =2 - one fourth (1/8 of clk), =3 - one eighth (1/16 of clk)
output reg [2:0] tst
); );
always @* wire req = cpu_req || dma_req;
if (stb) wire [7:0] din = dma_req ? dma_din : cpu_din;
tst = 5;
else if (start)
tst = 3;
else if (dma_req)
tst = 1;
else if (cpu_req)
tst = 4;
else tst = 0;
wire req = cpu_req || dma_req;
wire [7:0] din = dma_req ? dma_din : cpu_din;
//initial // for simulation only! // sdo is high bit of shiftout
//begin assign sdo = shiftout[7];
// counter = 5'b10000; wire ena_shout_load = (start || sck) & g_ena; // enable load of shiftout register
// shiftout = 8'd0; assign sck = counter[0];
// shiftout = 7'd0; wire rdy = counter[4]; // =0 when transmission in progress
// bsync = 1'd0; assign stb = stb_r && !rdy;
// dout = 1'b0; assign start = req && rdy;
//end
// sdo is high bit of shiftout reg [6:0] shiftin; // shifting in data from sdi before emitting it on dout
assign sdo = shiftout[7]; reg [4:0] counter; // handles transmission
wire ena_shout_load = (start || sck) & g_ena; // enable load of shiftout register reg stb_r;
assign sck = counter[0]; always @(posedge clk) begin
wire rdy = counter[4]; // =0 when transmission in progress if (g_ena) begin
assign stb = stb_r && !rdy; if (start) begin
assign start = req && rdy; counter <= 5'b0; // rdy = 0; sck = 0;
bsync <= 1'b1; // begin bsync pulse
reg [6:0] shiftin; // shifting in data from sdi before emitting it on dout stb_r <= 1'b0;
reg [4:0] counter; // handles transmission end
reg stb_r; else begin
always @(posedge clk) if (!sck) begin // on the rising edge of sck
begin shiftin[6:0] <= {shiftin[5:0], sdi};
if (g_ena) if (&counter[3:1] && !rdy) begin
begin dout <= {shiftin[6:0], sdi}; // update dout at the last sck rising edge
if (start) stb_r <= 1'b1;
begin
counter <= 5'b0; // rdy = 0; sck = 0;
bsync <= 1'b1; // begin bsync pulse
stb_r <= 1'b0;
end
else
begin
if (!sck) // on the rising edge of sck
begin
shiftin[6:0] <= {shiftin[5:0], sdi};
if (&counter[3:1] && !rdy)
begin
dout <= {shiftin[6:0], sdi}; // update dout at the last sck rising edge
stb_r <= 1'b1;
end
end end
else // on the falling edge of sck
begin
bsync <= 1'b0;
end
if (!rdy)
counter <= counter + 5'd1;
end end
else begin // on the falling edge of sck
bsync <= 1'b0;
end
if (!rdy) counter <= counter + 5'd1;
end end
end end
end
// shiftout treatment is done so just to save LCELLs in acex1k // shiftout treatment is done so just to save LCELLs in acex1k
reg [7:0] shiftout; // shifting out data to the sdo reg [7:0] shiftout; // shifting out data to the sdo
always @(posedge clk) always @(posedge clk) begin
begin if (ena_shout_load) begin
if (ena_shout_load) if (start) shiftout <= din;
begin else shiftout[7:0] <= {shiftout[6:0], shiftout[0]}; // last bit remains after end of exchange
if (start)
shiftout <= din;
else // sck
shiftout[7:0] <= {shiftout[6:0], shiftout[0]}; // last bit remains after end of exchange
end
end end
end
// slow speeds - controlled by g_ena
// slow speeds - controlled by g_ena reg [2:0] wcnt;
reg [2:0] wcnt; always @(posedge clk) begin
always @(posedge clk) if (|speed) begin
begin if (start) wcnt <= 1;
if (|speed) else if (rdy) wcnt <= 0;
begin else wcnt <= wcnt + 1'd1;
if (start)
wcnt <= 3'b001;
else if (rdy)
wcnt <= 3'b000;
else
wcnt <= wcnt + 3'd1;
end
else
wcnt <= 3'b000;
end end
else wcnt <= 0;
end
wire [3:0] g_en = {~|wcnt[2:0], ~|wcnt[1:0], ~|wcnt[0], 1'b1};
wire g_ena = g_en[speed]; wire g_ena = g_en[speed];
wire g_en[0:3];
assign g_en[0] = 1'b1;
assign g_en[1] = ~|wcnt[0];
assign g_en[2] = ~|wcnt[1:0];
assign g_en[3] = ~|wcnt[2:0];
endmodule endmodule

54
src/tsconf.v
View File

@ -296,7 +296,6 @@ wire [7:0] mouse_do;
clock TS01 clock TS01
( (
.clk(clk_28mhz), .clk(clk_28mhz),
.ay_mod(0),
.f0(f0), .f0(f0),
.f1(f1), .f1(f1),
.h0(h0), .h0(h0),
@ -304,8 +303,7 @@ clock TS01
.c0(c0), .c0(c0),
.c1(c1), .c1(c1),
.c2(c2), .c2(c2),
.c3(c3), .c3(c3)
.ce_saa(ce_saa)
); );
zclock TS02 zclock TS02
@ -330,11 +328,11 @@ T80s #(.mode(0), .t2write(1), .iowait(1)) z80_unit
( (
.reset_n((~reset)), .reset_n((~reset)),
.clk_n(zclk), .clk_n(zclk),
.cen(1'b1), .cen(1),
.wait_n(1'b1), .wait_n(1),
.int_n(cpu_int_n_TS), .int_n(cpu_int_n_TS),
.nmi_n(1'b1), .nmi_n(1),
.busrq_n(1'b1), .busrq_n(1),
.m1_n(cpu_m1_n), .m1_n(cpu_m1_n),
.mreq_n(cpu_mreq_n), .mreq_n(cpu_mreq_n),
.iorq_n(cpu_iorq_n), .iorq_n(cpu_iorq_n),
@ -438,12 +436,12 @@ zports TS05
.vdos_on(vdos_on), .vdos_on(vdos_on),
.vdos_off(vdos_off), .vdos_off(vdos_off),
.rstrom(2'b11), .rstrom(2'b11),
.tape_read(1'b1), .tape_read(1),
.keys_in(kb_do_bus), // keys (port FE) .keys_in(kb_do_bus), // keys (port FE)
.mus_in(mouse_do), // mouse (xxDF) .mus_in(mouse_do), // mouse (xxDF)
.kj_in(joystick), .kj_in(joystick),
.vg_intrq(1'b0), .vg_intrq(0),
.vg_drq(1'b0), // from vg93 module - drq + irq read .vg_drq(0), // from vg93 module - drq + irq read
.sdcs_n(SD_CS_N), // to SD card .sdcs_n(SD_CS_N), // to SD card
.sd_start(cpu_spi_req), // to SPI .sd_start(cpu_spi_req), // to SPI
.sd_datain(cpu_spi_din), // to SPI(7 downto 0); .sd_datain(cpu_spi_din), // to SPI(7 downto 0);
@ -453,7 +451,7 @@ zports TS05
.com_data_rx(8'b00000000), //uart_do_bus, .com_data_rx(8'b00000000), //uart_do_bus,
.com_status(8'b10010000), //'1' & uart_tx_empty & uart_tx_fifo_empty & "1000" & uart_rx_avail, .com_status(8'b10010000), //'1' & uart_tx_empty & uart_tx_fifo_empty & "1000" & uart_rx_avail,
//com_status=> '0' & uart_tx_empty & uart_tx_fifo_empty & "0000" & '1', //com_status=> '0' & uart_tx_empty & uart_tx_fifo_empty & "0000" & '1',
.lock_conf(1'b1) .lock_conf(1)
); );
zmem TS06 zmem TS06
@ -495,8 +493,8 @@ zmem TS06
.cpu_latch(cpu_latch), .cpu_latch(cpu_latch),
.cpu_stall(cpu_stall), // for Zclock if HI-> STALL (ZCLK) .cpu_stall(cpu_stall), // for Zclock if HI-> STALL (ZCLK)
.loader(0), // ROM for loader active .loader(0), // ROM for loader active
.testkey(1'b1), .testkey(1),
.intt(1'b0) .intt(0)
); );
arbiter TS07 arbiter TS07
@ -665,8 +663,7 @@ zmaps TS10
.cram_we(cram_we), .cram_we(cram_we),
.sfile_we(sfile_we) .sfile_we(sfile_we)
); );
spi TS11 spi TS11
( (
.clk(clk_28mhz), .clk(clk_28mhz),
@ -680,7 +677,7 @@ spi TS11
.cpu_req(cpu_spi_req), .cpu_req(cpu_spi_req),
.cpu_din(cpu_spi_din), .cpu_din(cpu_spi_din),
.dout(spi_dout), .dout(spi_dout),
.speed(2'b00) .speed(0)
); );
zint TS13 zint TS13
@ -738,7 +735,7 @@ sdram SE4
// PS/2 Keyboard // PS/2 Keyboard
wire [4:0] kb_do_bus; wire [4:0] kb_do_bus;
wire [4:0] kb_f_bus; wire key_reset;
wire [7:0] key_scancode; wire [7:0] key_scancode;
keyboard SE5 keyboard SE5
@ -747,7 +744,7 @@ keyboard SE5
.reset(COLD_RESET | WARM_RESET), .reset(COLD_RESET | WARM_RESET),
.a(cpu_a_bus[15:8]), .a(cpu_a_bus[15:8]),
.keyb(kb_do_bus), .keyb(kb_do_bus),
.keyf(kb_f_bus), .KEY_RESET(key_reset),
.scancode(key_scancode), .scancode(key_scancode),
.ps2_key(PS2_KEY) .ps2_key(PS2_KEY)
); );
@ -784,7 +781,7 @@ mc146818a SE9
.reset(reset), .reset(reset),
.clk(clk_28mhz), .clk(clk_28mhz),
.ena(ena_0_4375mhz), .ena(ena_0_4375mhz),
.cs(1'b1), .cs(1),
.keyscancode(key_scancode), .keyscancode(key_scancode),
.rtc(RTC), .rtc(RTC),
.cmoscfg(CMOSCfg), .cmoscfg(CMOSCfg),
@ -805,7 +802,7 @@ soundrive SE10
( (
.reset(reset), .reset(reset),
.clk(clk_28mhz), .clk(clk_28mhz),
.cs(1'b1), .cs(1),
.wr_n(cpu_wr_n), .wr_n(cpu_wr_n),
.a(cpu_a_bus[7:0]), .a(cpu_a_bus[7:0]),
.di(cpu_do_bus), .di(cpu_do_bus),
@ -891,15 +888,24 @@ gs #("src/sound/gs105b.mif") U15
// SAA1099 // SAA1099
wire [7:0] saa_out_l; wire [7:0] saa_out_l;
wire [7:0] saa_out_r; wire [7:0] saa_out_r;
wire ce_saa;
wire saa_wr_n = ~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFF && ~dos; wire saa_wr_n = ~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFF && ~dos;
reg ce_saa;
always @(posedge clk_28mhz) begin
reg [2:0] div;
div <= div + 1'd1;
if(div == 6) div <= 0;
ce_saa <= (div == 0 || div == 3);
end
saa1099 U16 saa1099 U16
( (
.clk_sys(clk_28mhz), .clk_sys(clk_28mhz),
.ce(ce_saa), .ce(ce_saa),
.rst_n((~reset)), .rst_n(~reset),
.cs_n(1'b0), .cs_n(0),
.a0(cpu_a_bus[8]), // 0=data, 1=address .a0(cpu_a_bus[8]), // 0=data, 1=address
.wr_n(saa_wr_n), .wr_n(saa_wr_n),
.din(cpu_do_bus), .din(cpu_do_bus),
@ -921,7 +927,7 @@ compressor compressor
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// Global // Global
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
wire reset = COLD_RESET | WARM_RESET | kb_f_bus[1]; // Reset wire reset = COLD_RESET | WARM_RESET | key_reset;
assign RESET_OUT = reset; assign RESET_OUT = reset;
// CPU interface // CPU interface