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https://github.com/UzixLS/TSConf_MiST.git
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always use cache for rom
This fixes Bomberman Evolution, which is (apparently) requires fast rom code execution
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@ -211,8 +211,9 @@ module zmem
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wire [13:0] cpu_hi_addr = {rom_n_ram, page[7:0], za[13:9]};
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wire [13:0] cpu_hi_addr = {rom_n_ram, page[7:0], za[13:9]};
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// wire cache_hit = (ch_addr[7:2] != 6'b011100) && (cpu_hi_addr == cache_a) && cache_v; // debug for BM
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// wire cache_hit = (ch_addr[7:2] != 6'b011100) && (cpu_hi_addr == cache_a) && cache_v; // debug for BM
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wire cache_hit = (cpu_hi_addr == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid
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wire cache_hit = (cpu_hi_addr == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid
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assign cache_hit_en = cache_hit && cache_en[win];
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assign cache_hit_en = cache_hit && (cache_en[win] || rom_n_ram);
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wire cache_inv = cache_hit && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address
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wire cache_inv = cache_hit && memwr_s && ramwr_en; // cache invalidation should be only performed if write happens to cached address
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wire cache_inv_rst = cache_inv || rst; // rst may happen at the same time with cpu_strobe, which leads incorrect data will be written to 0h address
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wire [7:0] ch_addr = cpu_addr[7:0];
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wire [7:0] ch_addr = cpu_addr[7:0];
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// wire [14:0] cpu_hi_addr = {page[7:0], za[13:7]};
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// wire [14:0] cpu_hi_addr = {page[7:0], za[13:7]};
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@ -233,7 +234,7 @@ module zmem
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(
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(
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.clock(clk),
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.clock(clk),
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.address_a(ch_addr),
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.address_a(ch_addr),
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.data_a({!cache_inv, cpu_hi_addr}),
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.data_a({!cache_inv_rst, cpu_hi_addr}),
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.wren_a(cpu_strobe || cache_inv),
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.wren_a(cpu_strobe || cache_inv),
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.address_b(ch_addr),
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.address_b(ch_addr),
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.q_b({cache_v, cache_a})
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.q_b({cache_v, cache_a})
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