mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
update T80
This commit is contained in:
205
rtl/T80/GBse.vhd
Normal file
205
rtl/T80/GBse.vhd
Normal file
@ -0,0 +1,205 @@
|
|||||||
|
-- ****
|
||||||
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
|
--
|
||||||
|
--
|
||||||
|
-- Ver 300 started tidyup
|
||||||
|
-- MikeJ March 2005
|
||||||
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
--
|
||||||
|
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||||
|
-- Different timing than the original z80
|
||||||
|
-- Inputs needs to be synchronous and outputs may glitch
|
||||||
|
--
|
||||||
|
-- Version : 0240
|
||||||
|
--
|
||||||
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
--
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
||||||
|
-- Please report bugs to the author, but before you do so, please
|
||||||
|
-- make sure that this is not a derivative work and that
|
||||||
|
-- you have the latest version of this file.
|
||||||
|
--
|
||||||
|
-- The latest version of this file can be found at:
|
||||||
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
|
--
|
||||||
|
-- Limitations :
|
||||||
|
--
|
||||||
|
-- File history :
|
||||||
|
--
|
||||||
|
-- 0235 : First release
|
||||||
|
--
|
||||||
|
-- 0236 : Added T2Write generic
|
||||||
|
--
|
||||||
|
-- 0237 : Fixed T2Write with wait state
|
||||||
|
--
|
||||||
|
-- 0238 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0240 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0242 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
use IEEE.numeric_std.all;
|
||||||
|
use work.T80_Pack.all;
|
||||||
|
|
||||||
|
entity GBse is
|
||||||
|
generic(
|
||||||
|
T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||||
|
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
RESET_n : in std_logic;
|
||||||
|
CLK_n : in std_logic;
|
||||||
|
CLKEN : in std_logic;
|
||||||
|
WAIT_n : in std_logic;
|
||||||
|
INT_n : in std_logic;
|
||||||
|
NMI_n : in std_logic;
|
||||||
|
BUSRQ_n : in std_logic;
|
||||||
|
M1_n : out std_logic;
|
||||||
|
MREQ_n : out std_logic;
|
||||||
|
IORQ_n : out std_logic;
|
||||||
|
RD_n : out std_logic;
|
||||||
|
WR_n : out std_logic;
|
||||||
|
RFSH_n : out std_logic;
|
||||||
|
HALT_n : out std_logic;
|
||||||
|
BUSAK_n : out std_logic;
|
||||||
|
STOP : out std_logic;
|
||||||
|
A : out std_logic_vector(15 downto 0);
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||||||
|
DI : in std_logic_vector(7 downto 0);
|
||||||
|
DO : out std_logic_vector(7 downto 0)
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||||||
|
);
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||||||
|
end GBse;
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||||||
|
|
||||||
|
architecture rtl of GBse is
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|
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|
signal IntCycle_n : std_logic;
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|
signal NoRead : std_logic;
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|
signal Write : std_logic;
|
||||||
|
signal IORQ : std_logic;
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|
signal DI_Reg : std_logic_vector(7 downto 0);
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||||||
|
signal MCycle : std_logic_vector(2 downto 0);
|
||||||
|
signal TState : std_logic_vector(2 downto 0);
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||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
u0 : T80
|
||||||
|
generic map(
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||||||
|
Mode => 3,
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||||||
|
IOWait => IOWait,
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||||||
|
Flag_S => 0,
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||||||
|
Flag_P => 0,
|
||||||
|
Flag_X => 0,
|
||||||
|
Flag_Y => 0,
|
||||||
|
Flag_C => 4,
|
||||||
|
Flag_H => 5,
|
||||||
|
Flag_N => 6,
|
||||||
|
Flag_Z => 7
|
||||||
|
)
|
||||||
|
port map(
|
||||||
|
CEN => CLKEN,
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||||||
|
M1_n => M1_n,
|
||||||
|
IORQ => IORQ,
|
||||||
|
NoRead => NoRead,
|
||||||
|
Write => Write,
|
||||||
|
RFSH_n => RFSH_n,
|
||||||
|
HALT_n => HALT_n,
|
||||||
|
Stop => STOP,
|
||||||
|
WAIT_n => Wait_n,
|
||||||
|
INT_n => INT_n,
|
||||||
|
NMI_n => NMI_n,
|
||||||
|
RESET_n => RESET_n,
|
||||||
|
BUSRQ_n => BUSRQ_n,
|
||||||
|
BUSAK_n => BUSAK_n,
|
||||||
|
CLK_n => CLK_n,
|
||||||
|
A => A,
|
||||||
|
DInst => DI,
|
||||||
|
DI => DI_Reg,
|
||||||
|
DO => DO,
|
||||||
|
MC => MCycle,
|
||||||
|
TS => TState,
|
||||||
|
IntCycle_n => IntCycle_n);
|
||||||
|
|
||||||
|
process (RESET_n, CLK_n)
|
||||||
|
begin
|
||||||
|
if RESET_n = '0' then
|
||||||
|
RD_n <= '1';
|
||||||
|
WR_n <= '1';
|
||||||
|
IORQ_n <= '1';
|
||||||
|
MREQ_n <= '1';
|
||||||
|
DI_Reg <= "00000000";
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
if CLKEN = '1' then
|
||||||
|
RD_n <= '1';
|
||||||
|
WR_n <= '1';
|
||||||
|
IORQ_n <= '1';
|
||||||
|
MREQ_n <= '1';
|
||||||
|
if MCycle = "001" then
|
||||||
|
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||||
|
RD_n <= not IntCycle_n;
|
||||||
|
MREQ_n <= not IntCycle_n;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
MREQ_n <= '0';
|
||||||
|
end if;
|
||||||
|
elsif MCycle = "011" and IntCycle_n = '0' then
|
||||||
|
if TState = "001" then
|
||||||
|
IORQ_n <= '0'; -- Acknowledge IRQ
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
|
||||||
|
RD_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
if T2Write = 0 then
|
||||||
|
if TState = "010" and Write = '1' then
|
||||||
|
WR_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
|
||||||
|
WR_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if TState = "010" and Wait_n = '1' then
|
||||||
|
DI_Reg <= DI;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end;
|
58
rtl/T80/README
Normal file
58
rtl/T80/README
Normal file
@ -0,0 +1,58 @@
|
|||||||
|
--------------------------------------------------------------------------------
|
||||||
|
-- ****
|
||||||
|
-- T80(c) core. Attempt to finish all undocumented features and provide
|
||||||
|
-- accurate timings.
|
||||||
|
--
|
||||||
|
-- Version 351.
|
||||||
|
-- Merged Gameboy fixes from Bruno Duarte Gouveia (brNX)
|
||||||
|
-- Passes Blargg's test ROMs
|
||||||
|
--
|
||||||
|
-- Version 350.
|
||||||
|
-- Copyright (c) 2018 Sorgelig
|
||||||
|
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
|
||||||
|
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
|
||||||
|
-- correct implementation is still unclear.
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
|
--
|
||||||
|
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
|
||||||
|
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
|
||||||
|
-- Ver 300 started tidyup.
|
||||||
|
--
|
||||||
|
-- MikeJ March 2005
|
||||||
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
-- Z80 compatible microprocessor core
|
||||||
|
--
|
||||||
|
-- Version : 0250
|
||||||
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
@ -1,6 +1,13 @@
|
|||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) GBse.vhd ]
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ]
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ]
|
||||||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80se.vhd ]
|
||||||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80a.vhd ]
|
||||||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80as.vhd ]
|
||||||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80sed.vhd ]
|
||||||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T8080se.vhd ]
|
||||||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ]
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ]
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ]
|
||||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ]
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ]
|
||||||
|
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Pack.vhd ]
|
1267
rtl/T80/T80.vhd
1267
rtl/T80/T80.vhd
File diff suppressed because it is too large
Load Diff
194
rtl/T80/T8080se.vhd
Normal file
194
rtl/T80/T8080se.vhd
Normal file
@ -0,0 +1,194 @@
|
|||||||
|
-- ****
|
||||||
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
|
--
|
||||||
|
--
|
||||||
|
-- Ver 300 started tidyup
|
||||||
|
-- MikeJ March 2005
|
||||||
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
--
|
||||||
|
-- 8080 compatible microprocessor core, synchronous top level with clock enable
|
||||||
|
-- Different timing than the original 8080
|
||||||
|
-- Inputs needs to be synchronous and outputs may glitch
|
||||||
|
--
|
||||||
|
-- Version : 0242
|
||||||
|
--
|
||||||
|
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
--
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
||||||
|
-- Please report bugs to the author, but before you do so, please
|
||||||
|
-- make sure that this is not a derivative work and that
|
||||||
|
-- you have the latest version of this file.
|
||||||
|
--
|
||||||
|
-- The latest version of this file can be found at:
|
||||||
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
|
--
|
||||||
|
-- Limitations :
|
||||||
|
-- STACK status output not supported
|
||||||
|
--
|
||||||
|
-- File history :
|
||||||
|
--
|
||||||
|
-- 0237 : First version
|
||||||
|
--
|
||||||
|
-- 0238 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0240 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0242 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
use IEEE.numeric_std.all;
|
||||||
|
use work.T80_Pack.all;
|
||||||
|
|
||||||
|
entity T8080se is
|
||||||
|
generic(
|
||||||
|
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||||
|
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
RESET_n : in std_logic;
|
||||||
|
CLK : in std_logic;
|
||||||
|
CLKEN : in std_logic;
|
||||||
|
READY : in std_logic;
|
||||||
|
HOLD : in std_logic;
|
||||||
|
INT : in std_logic;
|
||||||
|
INTE : out std_logic;
|
||||||
|
DBIN : out std_logic;
|
||||||
|
SYNC : out std_logic;
|
||||||
|
VAIT : out std_logic;
|
||||||
|
HLDA : out std_logic;
|
||||||
|
WR_n : out std_logic;
|
||||||
|
A : out std_logic_vector(15 downto 0);
|
||||||
|
DI : in std_logic_vector(7 downto 0);
|
||||||
|
DO : out std_logic_vector(7 downto 0)
|
||||||
|
);
|
||||||
|
end T8080se;
|
||||||
|
|
||||||
|
architecture rtl of T8080se is
|
||||||
|
|
||||||
|
signal IntCycle_n : std_logic;
|
||||||
|
signal NoRead : std_logic;
|
||||||
|
signal Write : std_logic;
|
||||||
|
signal IORQ : std_logic;
|
||||||
|
signal INT_n : std_logic;
|
||||||
|
signal HALT_n : std_logic;
|
||||||
|
signal BUSRQ_n : std_logic;
|
||||||
|
signal BUSAK_n : std_logic;
|
||||||
|
signal DO_i : std_logic_vector(7 downto 0);
|
||||||
|
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||||
|
signal MCycle : std_logic_vector(2 downto 0);
|
||||||
|
signal TState : std_logic_vector(2 downto 0);
|
||||||
|
signal One : std_logic;
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
INT_n <= not INT;
|
||||||
|
BUSRQ_n <= HOLD;
|
||||||
|
HLDA <= not BUSAK_n;
|
||||||
|
SYNC <= '1' when TState = "001" else '0';
|
||||||
|
VAIT <= '1' when TState = "010" else '0';
|
||||||
|
One <= '1';
|
||||||
|
|
||||||
|
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
|
||||||
|
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
|
||||||
|
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
|
||||||
|
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
|
||||||
|
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
|
||||||
|
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
|
||||||
|
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
|
||||||
|
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
|
||||||
|
|
||||||
|
u0 : T80
|
||||||
|
generic map(
|
||||||
|
Mode => Mode,
|
||||||
|
IOWait => 0)
|
||||||
|
port map(
|
||||||
|
CEN => CLKEN,
|
||||||
|
M1_n => open,
|
||||||
|
IORQ => IORQ,
|
||||||
|
NoRead => NoRead,
|
||||||
|
Write => Write,
|
||||||
|
RFSH_n => open,
|
||||||
|
HALT_n => HALT_n,
|
||||||
|
WAIT_n => READY,
|
||||||
|
INT_n => INT_n,
|
||||||
|
NMI_n => One,
|
||||||
|
RESET_n => RESET_n,
|
||||||
|
BUSRQ_n => One,
|
||||||
|
BUSAK_n => BUSAK_n,
|
||||||
|
CLK_n => CLK,
|
||||||
|
A => A,
|
||||||
|
DInst => DI,
|
||||||
|
DI => DI_Reg,
|
||||||
|
DO => DO_i,
|
||||||
|
MC => MCycle,
|
||||||
|
TS => TState,
|
||||||
|
IntCycle_n => IntCycle_n,
|
||||||
|
IntE => INTE);
|
||||||
|
|
||||||
|
process (RESET_n, CLK)
|
||||||
|
begin
|
||||||
|
if RESET_n = '0' then
|
||||||
|
DBIN <= '0';
|
||||||
|
WR_n <= '1';
|
||||||
|
DI_Reg <= "00000000";
|
||||||
|
elsif CLK'event and CLK = '1' then
|
||||||
|
if CLKEN = '1' then
|
||||||
|
DBIN <= '0';
|
||||||
|
WR_n <= '1';
|
||||||
|
if MCycle = "001" then
|
||||||
|
if TState = "001" or (TState = "010" and READY = '0') then
|
||||||
|
DBIN <= IntCycle_n;
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
|
||||||
|
DBIN <= '1';
|
||||||
|
end if;
|
||||||
|
if T2Write = 0 then
|
||||||
|
if TState = "010" and Write = '1' then
|
||||||
|
WR_n <= '0';
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
|
||||||
|
WR_n <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if TState = "010" and READY = '1' then
|
||||||
|
DI_Reg <= DI;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end;
|
@ -1,13 +1,13 @@
|
|||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
-- ****
|
-- ****
|
||||||
-- T80(c) core. Attempt to finish all undocumented features and provide
|
-- T80(c) core. Attempt to finish all undocumented features and provide
|
||||||
-- accurate timings.
|
-- accurate timings.
|
||||||
-- Version 350.
|
-- Version 350.
|
||||||
-- Copyright (c) 2018 Sorgelig
|
-- Copyright (c) 2018 Sorgelig
|
||||||
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
|
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
|
||||||
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
|
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
|
||||||
-- correct implementation is still unclear.
|
-- correct implementation is still unclear.
|
||||||
--
|
--
|
||||||
-- ****
|
-- ****
|
||||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
--
|
--
|
||||||
@ -86,9 +86,10 @@ entity T80_ALU is
|
|||||||
port(
|
port(
|
||||||
Arith16 : in std_logic;
|
Arith16 : in std_logic;
|
||||||
Z16 : in std_logic;
|
Z16 : in std_logic;
|
||||||
WZ : in std_logic_vector(15 downto 0);
|
WZ : in std_logic_vector(15 downto 0);
|
||||||
XY_State : in std_logic_vector(1 downto 0);
|
XY_State : in std_logic_vector(1 downto 0);
|
||||||
ALU_Op : in std_logic_vector(3 downto 0);
|
ALU_Op : in std_logic_vector(3 downto 0);
|
||||||
|
Rot_Akku : in std_logic;
|
||||||
IR : in std_logic_vector(5 downto 0);
|
IR : in std_logic_vector(5 downto 0);
|
||||||
ISet : in std_logic_vector(1 downto 0);
|
ISet : in std_logic_vector(1 downto 0);
|
||||||
BusA : in std_logic_vector(7 downto 0);
|
BusA : in std_logic_vector(7 downto 0);
|
||||||
@ -158,7 +159,7 @@ begin
|
|||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, WZ, XY_State)
|
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16, Rot_Akku, WZ, XY_State)
|
||||||
variable Q_t : std_logic_vector(7 downto 0);
|
variable Q_t : std_logic_vector(7 downto 0);
|
||||||
variable DAA_Q : unsigned(8 downto 0);
|
variable DAA_Q : unsigned(8 downto 0);
|
||||||
begin
|
begin
|
||||||
@ -220,35 +221,64 @@ begin
|
|||||||
end if;
|
end if;
|
||||||
when "1100" =>
|
when "1100" =>
|
||||||
-- DAA
|
-- DAA
|
||||||
F_Out(Flag_H) <= F_In(Flag_H);
|
if Mode = 3 then
|
||||||
F_Out(Flag_C) <= F_In(Flag_C);
|
F_Out(Flag_H) <= '0';
|
||||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
F_Out(Flag_C) <= F_In(Flag_C);
|
||||||
DAA_Q(8) := '0';
|
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||||
if F_In(Flag_N) = '0' then
|
DAA_Q(8) := '0';
|
||||||
-- After addition
|
if F_In(Flag_N) = '0' then
|
||||||
-- Alow > 9 or H = 1
|
-- After addition
|
||||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
-- Alow > 9 or H = 1
|
||||||
if (DAA_Q(3 downto 0) > 9) then
|
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||||
F_Out(Flag_H) <= '1';
|
DAA_Q := DAA_Q + 6;
|
||||||
else
|
end if;
|
||||||
F_Out(Flag_H) <= '0';
|
-- new Ahigh > 9 or C = 1
|
||||||
|
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||||
|
DAA_Q := DAA_Q + 96; -- 0x60
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
-- After subtraction
|
||||||
|
if F_In(Flag_H) = '1' then
|
||||||
|
DAA_Q := DAA_Q - 6;
|
||||||
|
if F_In(Flag_C) = '0' then
|
||||||
|
DAA_Q(8) := '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if F_In(Flag_C) = '1' then
|
||||||
|
DAA_Q := DAA_Q - 96; -- 0x60
|
||||||
end if;
|
end if;
|
||||||
DAA_Q := DAA_Q + 6;
|
|
||||||
end if;
|
|
||||||
-- new Ahigh > 9 or C = 1
|
|
||||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
|
||||||
DAA_Q := DAA_Q + 96; -- 0x60
|
|
||||||
end if;
|
end if;
|
||||||
else
|
else
|
||||||
-- After subtraction
|
F_Out(Flag_H) <= F_In(Flag_H);
|
||||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
F_Out(Flag_C) <= F_In(Flag_C);
|
||||||
if DAA_Q(3 downto 0) > 5 then
|
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||||
F_Out(Flag_H) <= '0';
|
DAA_Q(8) := '0';
|
||||||
|
if F_In(Flag_N) = '0' then
|
||||||
|
-- After addition
|
||||||
|
-- Alow > 9 or H = 1
|
||||||
|
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||||
|
if (DAA_Q(3 downto 0) > 9) then
|
||||||
|
F_Out(Flag_H) <= '1';
|
||||||
|
else
|
||||||
|
F_Out(Flag_H) <= '0';
|
||||||
|
end if;
|
||||||
|
DAA_Q := DAA_Q + 6;
|
||||||
|
end if;
|
||||||
|
-- new Ahigh > 9 or C = 1
|
||||||
|
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||||
|
DAA_Q := DAA_Q + 96; -- 0x60
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
-- After subtraction
|
||||||
|
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||||
|
if DAA_Q(3 downto 0) > 5 then
|
||||||
|
F_Out(Flag_H) <= '0';
|
||||||
|
end if;
|
||||||
|
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||||
|
end if;
|
||||||
|
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||||
|
DAA_Q := DAA_Q - 352; -- 0x160
|
||||||
end if;
|
end if;
|
||||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
|
||||||
end if;
|
|
||||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
|
||||||
DAA_Q := DAA_Q - 352; -- 0x160
|
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
F_Out(Flag_X) <= DAA_Q(3);
|
F_Out(Flag_X) <= DAA_Q(3);
|
||||||
@ -297,11 +327,11 @@ begin
|
|||||||
F_Out(Flag_H) <= '1';
|
F_Out(Flag_H) <= '1';
|
||||||
F_Out(Flag_N) <= '0';
|
F_Out(Flag_N) <= '0';
|
||||||
if IR(2 downto 0) = "110" or XY_State /= "00" then
|
if IR(2 downto 0) = "110" or XY_State /= "00" then
|
||||||
F_Out(Flag_X) <= WZ(11);
|
F_Out(Flag_X) <= WZ(11);
|
||||||
F_Out(Flag_Y) <= WZ(13);
|
F_Out(Flag_Y) <= WZ(13);
|
||||||
else
|
else
|
||||||
F_Out(Flag_X) <= BusB(3);
|
F_Out(Flag_X) <= BusB(3);
|
||||||
F_Out(Flag_Y) <= BusB(5);
|
F_Out(Flag_Y) <= BusB(5);
|
||||||
end if;
|
end if;
|
||||||
when "1010" =>
|
when "1010" =>
|
||||||
-- SET
|
-- SET
|
||||||
@ -368,6 +398,9 @@ begin
|
|||||||
F_Out(Flag_S) <= F_In(Flag_S);
|
F_Out(Flag_S) <= F_In(Flag_S);
|
||||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||||
end if;
|
end if;
|
||||||
|
if Mode = 3 and Rot_Akku = '1' then
|
||||||
|
F_Out(Flag_Z) <= '0';
|
||||||
|
end if;
|
||||||
when others =>
|
when others =>
|
||||||
null;
|
null;
|
||||||
end case;
|
end case;
|
||||||
|
File diff suppressed because it is too large
Load Diff
248
rtl/T80/T80_Pack.vhd
Normal file
248
rtl/T80/T80_Pack.vhd
Normal file
@ -0,0 +1,248 @@
|
|||||||
|
-- ****
|
||||||
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
|
--
|
||||||
|
--
|
||||||
|
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
|
||||||
|
-- Ver 300 started tidyup
|
||||||
|
-- MikeJ March 2005
|
||||||
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
--
|
||||||
|
-- Z80 compatible microprocessor core
|
||||||
|
--
|
||||||
|
-- Version : 0250
|
||||||
|
--
|
||||||
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
--
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
||||||
|
-- Please report bugs to the author, but before you do so, please
|
||||||
|
-- make sure that this is not a derivative work and that
|
||||||
|
-- you have the latest version of this file.
|
||||||
|
--
|
||||||
|
-- The latest version of this file can be found at:
|
||||||
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
|
--
|
||||||
|
-- Limitations :
|
||||||
|
--
|
||||||
|
-- File history :
|
||||||
|
--
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
package T80_Pack is
|
||||||
|
|
||||||
|
constant aNone : std_logic_vector(2 downto 0) := "111";
|
||||||
|
constant aBC : std_logic_vector(2 downto 0) := "000";
|
||||||
|
constant aDE : std_logic_vector(2 downto 0) := "001";
|
||||||
|
constant aXY : std_logic_vector(2 downto 0) := "010";
|
||||||
|
constant aIOA : std_logic_vector(2 downto 0) := "100";
|
||||||
|
constant aSP : std_logic_vector(2 downto 0) := "101";
|
||||||
|
constant aZI : std_logic_vector(2 downto 0) := "110";
|
||||||
|
|
||||||
|
component T80
|
||||||
|
generic(
|
||||||
|
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||||
|
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||||
|
Flag_C : integer := 0;
|
||||||
|
Flag_N : integer := 1;
|
||||||
|
Flag_P : integer := 2;
|
||||||
|
Flag_X : integer := 3;
|
||||||
|
Flag_H : integer := 4;
|
||||||
|
Flag_Y : integer := 5;
|
||||||
|
Flag_Z : integer := 6;
|
||||||
|
Flag_S : integer := 7
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
RESET_n : in std_logic;
|
||||||
|
CLK_n : in std_logic;
|
||||||
|
CEN : in std_logic;
|
||||||
|
WAIT_n : in std_logic;
|
||||||
|
INT_n : in std_logic;
|
||||||
|
NMI_n : in std_logic;
|
||||||
|
BUSRQ_n : in std_logic;
|
||||||
|
M1_n : out std_logic;
|
||||||
|
IORQ : out std_logic;
|
||||||
|
NoRead : out std_logic;
|
||||||
|
Write : out std_logic;
|
||||||
|
RFSH_n : out std_logic;
|
||||||
|
HALT_n : out std_logic;
|
||||||
|
BUSAK_n : out std_logic;
|
||||||
|
A : out std_logic_vector(15 downto 0);
|
||||||
|
DInst : in std_logic_vector(7 downto 0);
|
||||||
|
DI : in std_logic_vector(7 downto 0);
|
||||||
|
DO : out std_logic_vector(7 downto 0);
|
||||||
|
MC : out std_logic_vector(2 downto 0);
|
||||||
|
TS : out std_logic_vector(2 downto 0);
|
||||||
|
IntCycle_n : out std_logic;
|
||||||
|
IntE : out std_logic;
|
||||||
|
Stop : out std_logic;
|
||||||
|
R800_mode : in std_logic := '0';
|
||||||
|
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
|
||||||
|
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
|
||||||
|
DIRSet : in std_logic := '0';
|
||||||
|
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
|
||||||
|
);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
component T80_Reg
|
||||||
|
port(
|
||||||
|
Clk : in std_logic;
|
||||||
|
CEN : in std_logic;
|
||||||
|
WEH : in std_logic;
|
||||||
|
WEL : in std_logic;
|
||||||
|
AddrA : in std_logic_vector(2 downto 0);
|
||||||
|
AddrB : in std_logic_vector(2 downto 0);
|
||||||
|
AddrC : in std_logic_vector(2 downto 0);
|
||||||
|
DIH : in std_logic_vector(7 downto 0);
|
||||||
|
DIL : in std_logic_vector(7 downto 0);
|
||||||
|
DOAH : out std_logic_vector(7 downto 0);
|
||||||
|
DOAL : out std_logic_vector(7 downto 0);
|
||||||
|
DOBH : out std_logic_vector(7 downto 0);
|
||||||
|
DOBL : out std_logic_vector(7 downto 0);
|
||||||
|
DOCH : out std_logic_vector(7 downto 0);
|
||||||
|
DOCL : out std_logic_vector(7 downto 0);
|
||||||
|
DOR : out std_logic_vector(127 downto 0);
|
||||||
|
DIRSet : in std_logic;
|
||||||
|
DIR : in std_logic_vector(127 downto 0)
|
||||||
|
);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
component T80_MCode
|
||||||
|
generic(
|
||||||
|
Mode : integer := 0;
|
||||||
|
Flag_C : integer := 0;
|
||||||
|
Flag_N : integer := 1;
|
||||||
|
Flag_P : integer := 2;
|
||||||
|
Flag_X : integer := 3;
|
||||||
|
Flag_H : integer := 4;
|
||||||
|
Flag_Y : integer := 5;
|
||||||
|
Flag_Z : integer := 6;
|
||||||
|
Flag_S : integer := 7
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
IR : in std_logic_vector(7 downto 0);
|
||||||
|
ISet : in std_logic_vector(1 downto 0);
|
||||||
|
MCycle : in std_logic_vector(2 downto 0);
|
||||||
|
F : in std_logic_vector(7 downto 0);
|
||||||
|
NMICycle : in std_logic;
|
||||||
|
IntCycle : in std_logic;
|
||||||
|
XY_State : in std_logic_vector(1 downto 0);
|
||||||
|
MCycles : out std_logic_vector(2 downto 0);
|
||||||
|
TStates : out std_logic_vector(2 downto 0);
|
||||||
|
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||||
|
Inc_PC : out std_logic;
|
||||||
|
Inc_WZ : out std_logic;
|
||||||
|
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||||
|
Read_To_Reg : out std_logic;
|
||||||
|
Read_To_Acc : out std_logic;
|
||||||
|
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||||
|
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||||
|
ALU_Op : out std_logic_vector(3 downto 0);
|
||||||
|
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||||
|
Save_ALU : out std_logic;
|
||||||
|
Rot_Akku : out std_logic;
|
||||||
|
PreserveC : out std_logic;
|
||||||
|
Arith16 : out std_logic;
|
||||||
|
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||||
|
IORQ : out std_logic;
|
||||||
|
Jump : out std_logic;
|
||||||
|
JumpE : out std_logic;
|
||||||
|
JumpXY : out std_logic;
|
||||||
|
Call : out std_logic;
|
||||||
|
RstP : out std_logic;
|
||||||
|
LDZ : out std_logic;
|
||||||
|
LDW : out std_logic;
|
||||||
|
LDSPHL : out std_logic;
|
||||||
|
LDHLSP : out std_logic;
|
||||||
|
ADDSPdd : out std_logic;
|
||||||
|
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||||
|
ExchangeDH : out std_logic;
|
||||||
|
ExchangeRp : out std_logic;
|
||||||
|
ExchangeAF : out std_logic;
|
||||||
|
ExchangeRS : out std_logic;
|
||||||
|
ExchangeWH : out std_logic;
|
||||||
|
I_DJNZ : out std_logic;
|
||||||
|
I_CPL : out std_logic;
|
||||||
|
I_CCF : out std_logic;
|
||||||
|
I_SCF : out std_logic;
|
||||||
|
I_RETN : out std_logic;
|
||||||
|
I_BT : out std_logic;
|
||||||
|
I_BC : out std_logic;
|
||||||
|
I_BTR : out std_logic;
|
||||||
|
I_RLD : out std_logic;
|
||||||
|
I_RRD : out std_logic;
|
||||||
|
I_INRC : out std_logic;
|
||||||
|
I_MULUB : out std_logic;
|
||||||
|
I_MULU : out std_logic;
|
||||||
|
SetWZ : out std_logic_vector(1 downto 0);
|
||||||
|
SetDI : out std_logic;
|
||||||
|
SetEI : out std_logic;
|
||||||
|
IMode : out std_logic_vector(1 downto 0);
|
||||||
|
Halt : out std_logic;
|
||||||
|
NoRead : out std_logic;
|
||||||
|
Write : out std_logic;
|
||||||
|
R800_mode : in std_logic;
|
||||||
|
No_PC : out std_logic;
|
||||||
|
XYbit_undoc : out std_logic
|
||||||
|
);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
component T80_ALU
|
||||||
|
generic(
|
||||||
|
Mode : integer := 0;
|
||||||
|
Flag_C : integer := 0;
|
||||||
|
Flag_N : integer := 1;
|
||||||
|
Flag_P : integer := 2;
|
||||||
|
Flag_X : integer := 3;
|
||||||
|
Flag_H : integer := 4;
|
||||||
|
Flag_Y : integer := 5;
|
||||||
|
Flag_Z : integer := 6;
|
||||||
|
Flag_S : integer := 7
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
Arith16 : in std_logic;
|
||||||
|
Z16 : in std_logic;
|
||||||
|
WZ : in std_logic_vector(15 downto 0);
|
||||||
|
XY_State : in std_logic_vector(1 downto 0);
|
||||||
|
ALU_Op : in std_logic_vector(3 downto 0);
|
||||||
|
Rot_Akku : in std_logic;
|
||||||
|
IR : in std_logic_vector(5 downto 0);
|
||||||
|
ISet : in std_logic_vector(1 downto 0);
|
||||||
|
BusA : in std_logic_vector(7 downto 0);
|
||||||
|
BusB : in std_logic_vector(7 downto 0);
|
||||||
|
F_In : in std_logic_vector(7 downto 0);
|
||||||
|
Q : out std_logic_vector(7 downto 0);
|
||||||
|
F_Out : out std_logic_vector(7 downto 0)
|
||||||
|
);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
end;
|
@ -1,13 +1,13 @@
|
|||||||
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
||||||
-- ****
|
-- ****
|
||||||
-- T80(c) core. Attempt to finish all undocumented features and provide
|
-- T80(c) core. Attempt to finish all undocumented features and provide
|
||||||
-- accurate timings.
|
-- accurate timings.
|
||||||
-- Version 350.
|
-- Version 350.
|
||||||
-- Copyright (c) 2018 Sorgelig
|
-- Copyright (c) 2018 Sorgelig
|
||||||
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
|
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
|
||||||
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
|
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
|
||||||
-- correct implementation is still unclear.
|
-- correct implementation is still unclear.
|
||||||
--
|
--
|
||||||
-- ****
|
-- ****
|
||||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
--
|
--
|
||||||
@ -89,7 +89,9 @@ entity T80_Reg is
|
|||||||
DOBL : out std_logic_vector(7 downto 0);
|
DOBL : out std_logic_vector(7 downto 0);
|
||||||
DOCH : out std_logic_vector(7 downto 0);
|
DOCH : out std_logic_vector(7 downto 0);
|
||||||
DOCL : out std_logic_vector(7 downto 0);
|
DOCL : out std_logic_vector(7 downto 0);
|
||||||
DOR : out std_logic_vector(127 downto 0)
|
DOR : out std_logic_vector(127 downto 0);
|
||||||
|
DIRSet : in std_logic;
|
||||||
|
DIR : in std_logic_vector(127 downto 0)
|
||||||
);
|
);
|
||||||
end T80_Reg;
|
end T80_Reg;
|
||||||
|
|
||||||
@ -104,7 +106,31 @@ begin
|
|||||||
process (Clk)
|
process (Clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(Clk) then
|
if rising_edge(Clk) then
|
||||||
if CEN = '1' then
|
if DIRSet = '1' then
|
||||||
|
RegsL(0) <= DIR( 7 downto 0);
|
||||||
|
RegsH(0) <= DIR( 15 downto 8);
|
||||||
|
|
||||||
|
RegsL(1) <= DIR( 23 downto 16);
|
||||||
|
RegsH(1) <= DIR( 31 downto 24);
|
||||||
|
|
||||||
|
RegsL(2) <= DIR( 39 downto 32);
|
||||||
|
RegsH(2) <= DIR( 47 downto 40);
|
||||||
|
|
||||||
|
RegsL(3) <= DIR( 55 downto 48);
|
||||||
|
RegsH(3) <= DIR( 63 downto 56);
|
||||||
|
|
||||||
|
RegsL(4) <= DIR( 71 downto 64);
|
||||||
|
RegsH(4) <= DIR( 79 downto 72);
|
||||||
|
|
||||||
|
RegsL(5) <= DIR( 87 downto 80);
|
||||||
|
RegsH(5) <= DIR( 95 downto 88);
|
||||||
|
|
||||||
|
RegsL(6) <= DIR(103 downto 96);
|
||||||
|
RegsH(6) <= DIR(111 downto 104);
|
||||||
|
|
||||||
|
RegsL(7) <= DIR(119 downto 112);
|
||||||
|
RegsH(7) <= DIR(127 downto 120);
|
||||||
|
elsif CEN = '1' then
|
||||||
if WEH = '1' then
|
if WEH = '1' then
|
||||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||||
end if;
|
end if;
|
||||||
|
342
rtl/T80/T80a.vhd
Normal file
342
rtl/T80/T80a.vhd
Normal file
@ -0,0 +1,342 @@
|
|||||||
|
-- ****
|
||||||
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
|
--
|
||||||
|
--
|
||||||
|
-- Ver 300 started tidyup
|
||||||
|
-- MikeJ March 2005
|
||||||
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
--
|
||||||
|
-- Z80 compatible microprocessor core, asynchronous top level
|
||||||
|
--
|
||||||
|
-- Version : 0250
|
||||||
|
--
|
||||||
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
--
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
||||||
|
-- Please report bugs to the author, but before you do so, please
|
||||||
|
-- make sure that this is not a derivative work and that
|
||||||
|
-- you have the latest version of this file.
|
||||||
|
--
|
||||||
|
-- The latest version of this file can be found at:
|
||||||
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
|
--
|
||||||
|
-- Limitations :
|
||||||
|
--
|
||||||
|
-- File history :
|
||||||
|
--
|
||||||
|
-- 0208 : First complete release
|
||||||
|
--
|
||||||
|
-- 0211 : Fixed interrupt cycle
|
||||||
|
--
|
||||||
|
-- 0235 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0238 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0240 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0242 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0247 : Fixed bus req/ack cycle
|
||||||
|
--
|
||||||
|
-- 0250 : Added R800 Multiplier by TobiFlex 2017.10.15
|
||||||
|
--
|
||||||
|
-- Bus signal logic changes from the ZX Spectrum Next were made by:
|
||||||
|
--
|
||||||
|
-- Fabio Belavenuto, Charlie Ingley
|
||||||
|
--
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
use IEEE.numeric_std.all;
|
||||||
|
use work.T80_Pack.all;
|
||||||
|
|
||||||
|
entity T80a is
|
||||||
|
generic(
|
||||||
|
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||||
|
IOWait : integer := 1 -- 0 => Single I/O cycle, 1 => Std I/O cycle
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
RESET_n : in std_logic;
|
||||||
|
R800_mode : in std_logic;
|
||||||
|
CLK_n : in std_logic;
|
||||||
|
WAIT_n : in std_logic;
|
||||||
|
INT_n : in std_logic;
|
||||||
|
NMI_n : in std_logic;
|
||||||
|
BUSRQ_n : in std_logic;
|
||||||
|
M1_n : out std_logic;
|
||||||
|
MREQ_n : out std_logic;
|
||||||
|
IORQ_n : out std_logic;
|
||||||
|
RD_n : out std_logic;
|
||||||
|
WR_n : out std_logic;
|
||||||
|
RFSH_n : out std_logic;
|
||||||
|
HALT_n : out std_logic;
|
||||||
|
BUSAK_n : out std_logic;
|
||||||
|
A : out std_logic_vector(15 downto 0);
|
||||||
|
D : inout std_logic_vector(7 downto 0)
|
||||||
|
);
|
||||||
|
end T80a;
|
||||||
|
|
||||||
|
architecture rtl of T80a is
|
||||||
|
|
||||||
|
signal CEN : std_logic;
|
||||||
|
signal Reset_s : std_logic;
|
||||||
|
signal IntCycle_n : std_logic;
|
||||||
|
signal IORQ : std_logic;
|
||||||
|
signal NoRead : std_logic;
|
||||||
|
signal Write : std_logic;
|
||||||
|
signal MREQ : std_logic;
|
||||||
|
signal MReq_Inhibit : std_logic;
|
||||||
|
signal Req_Inhibit : std_logic;
|
||||||
|
signal RD : std_logic;
|
||||||
|
signal MREQ_n_i : std_logic;
|
||||||
|
signal MREQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add MREQ control
|
||||||
|
signal IORQ_n_i : std_logic;
|
||||||
|
signal IORQ_t1 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
|
||||||
|
signal IORQ_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
|
||||||
|
signal IORQ_rw : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ control
|
||||||
|
signal IORQ_int : std_logic; -- 30/10/19 Charlie Ingley-- add IORQ interrupt control
|
||||||
|
signal IORQ_int_inhibit : std_logic_vector(2 downto 0);
|
||||||
|
signal RD_n_i : std_logic;
|
||||||
|
signal WR_n_i : std_logic;
|
||||||
|
signal WR_t2 : std_logic; -- 30/10/19 Charlie Ingley-- add WR control
|
||||||
|
signal RFSH_n_i : std_logic;
|
||||||
|
signal BUSAK_n_i : std_logic;
|
||||||
|
signal A_i : std_logic_vector(15 downto 0);
|
||||||
|
signal DO : std_logic_vector(7 downto 0);
|
||||||
|
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
|
||||||
|
signal Wait_s : std_logic;
|
||||||
|
signal MCycle : std_logic_vector(2 downto 0);
|
||||||
|
signal TState : std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
CEN <= '1';
|
||||||
|
|
||||||
|
BUSAK_n <= BUSAK_n_i; -- 30/10/19 Charlie Ingley - IORQ/RD/WR changes
|
||||||
|
MREQ_rw <= MREQ and (Req_Inhibit or MReq_Inhibit); -- added MREQ timing control
|
||||||
|
MREQ_n_i <= not MREQ_rw; -- changed MREQ generation
|
||||||
|
IORQ_rw <= IORQ and not (IORQ_t1 or IORQ_t2); -- added IORQ generation timing control
|
||||||
|
IORQ_n_i <= not ((IORQ_int and not IORQ_int_inhibit(2)) or IORQ_rw); -- changed IORQ generation
|
||||||
|
RD_n_i <= not (RD and (MREQ_rw or IORQ_rw)); -- changed RD/IORQ generation
|
||||||
|
WR_n_i <= not (Write and ((WR_t2 and MREQ_rw) or IORQ_rw)); -- added WR/IORQ timing control
|
||||||
|
|
||||||
|
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
|
||||||
|
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
|
||||||
|
|
||||||
|
process (RESET_n, CLK_n)
|
||||||
|
begin
|
||||||
|
if RESET_n = '0' then
|
||||||
|
Reset_s <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
Reset_s <= '1';
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
u0 : T80
|
||||||
|
generic map(
|
||||||
|
Mode => Mode,
|
||||||
|
IOWait => IOWait)
|
||||||
|
port map(
|
||||||
|
R800_mode => R800_mode,
|
||||||
|
CEN => CEN,
|
||||||
|
M1_n => M1_n,
|
||||||
|
IORQ => IORQ,
|
||||||
|
NoRead => NoRead,
|
||||||
|
Write => Write,
|
||||||
|
RFSH_n => RFSH_n_i,
|
||||||
|
HALT_n => HALT_n,
|
||||||
|
WAIT_n => Wait_s,
|
||||||
|
INT_n => INT_n,
|
||||||
|
NMI_n => NMI_n,
|
||||||
|
RESET_n => Reset_s,
|
||||||
|
BUSRQ_n => BUSRQ_n,
|
||||||
|
BUSAK_n => BUSAK_n_i,
|
||||||
|
CLK_n => CLK_n,
|
||||||
|
A => A_i,
|
||||||
|
DInst => D,
|
||||||
|
DI => DI_Reg,
|
||||||
|
DO => DO,
|
||||||
|
MC => MCycle,
|
||||||
|
TS => TState,
|
||||||
|
IntCycle_n => IntCycle_n);
|
||||||
|
|
||||||
|
process (CLK_n)
|
||||||
|
begin
|
||||||
|
if CLK_n'event and CLK_n = '0' then
|
||||||
|
Wait_s <= WAIT_n;
|
||||||
|
if TState = "011" and BUSAK_n_i = '1' then
|
||||||
|
DI_Reg <= to_x01(D);
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- 30/10/19 Charlie Ingley - Generate WR_t2 to correct MREQ/WR timing
|
||||||
|
process (Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
WR_t2 <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
if MCycle /= "001" then
|
||||||
|
if TState = "010" then -- WR starts on falling edge of T2 for MREQ
|
||||||
|
WR_t2 <= Write;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then -- end WR
|
||||||
|
WR_t2 <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- Generate Req_Inhibit
|
||||||
|
process (Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
Req_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
|
||||||
|
Req_Inhibit <= '0';
|
||||||
|
else
|
||||||
|
Req_Inhibit <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- Generate MReq_Inhibit
|
||||||
|
process (Reset_s, CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
MReq_Inhibit <= '1'; -- Charlie Ingley 30/10/19 - changed Req_Inhibit polarity
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
if MCycle = "001" and TState = "010" and WAIT_n = '1' then -- by Fabio Belavenuto - fix behavior of Wait_n
|
||||||
|
MReq_Inhibit <= '0';
|
||||||
|
else
|
||||||
|
MReq_Inhibit <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- Generate RD for MREQ
|
||||||
|
process(Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
RD <= '0';
|
||||||
|
MREQ <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
if MCycle = "001" then
|
||||||
|
if TState = "001" then
|
||||||
|
RD <= IntCycle_n;
|
||||||
|
MREQ <= IntCycle_n;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
RD <= '0';
|
||||||
|
MREQ <= '1';
|
||||||
|
end if;
|
||||||
|
if TState = "100" then
|
||||||
|
MREQ <= '0';
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if TState = "001" and NoRead = '0' then
|
||||||
|
RD <= not Write;
|
||||||
|
MREQ <= not IORQ;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
RD <= '0';
|
||||||
|
MREQ <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- 30/10/19 Charlie Ingley - Generate IORQ_int for IORQ interrupt timing control
|
||||||
|
process(Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
IORQ_int <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
if MCycle = "001" then
|
||||||
|
if TState = "001" then
|
||||||
|
IORQ_int <= not IntCycle_n;
|
||||||
|
end if;
|
||||||
|
if TState = "010" and Wait_s = '1' then
|
||||||
|
IORQ_int <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process(Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
IORQ_int_inhibit <= "111";
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
if IntCycle_n = '0' then
|
||||||
|
if MCycle = "001" then
|
||||||
|
IORQ_int_inhibit <= IORQ_int_inhibit(1 downto 0) & '0';
|
||||||
|
end if;
|
||||||
|
if MCycle = "010" then
|
||||||
|
IORQ_int_inhibit <= "111";
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- 30/10/19 Charlie Ingley - Generate IORQ_t1 for IORQ timing control
|
||||||
|
process(Reset_s, CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
IORQ_t1 <= '1';
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
if TState = "001" then
|
||||||
|
IORQ_t1 <= not IntCycle_n;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
IORQ_t1 <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
-- 30/10/19 Charlie Ingley - Generate IORQ_t2 for IORQ timing control
|
||||||
|
process (RESET_n, CLK_n)
|
||||||
|
begin
|
||||||
|
if RESET_n = '0' then
|
||||||
|
IORQ_t2 <= '1';
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
IORQ_t2 <= IORQ_t1;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end;
|
289
rtl/T80/T80as.vhd
Normal file
289
rtl/T80/T80as.vhd
Normal file
@ -0,0 +1,289 @@
|
|||||||
|
------------------------------------------------------------------------------
|
||||||
|
-- 2004.10.18 WR_n active was changed from T2 to T3.
|
||||||
|
-- modification by Katsumi Degawa
|
||||||
|
------------------------------------------------------------------------------
|
||||||
|
-- t80as.vhd : The non-tristate signal edition of t80a.vhd
|
||||||
|
--
|
||||||
|
-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
|
||||||
|
--
|
||||||
|
-- 1.separate 'D' to 'DO' and 'DI'.
|
||||||
|
-- 2.added 'DOE' to 'DO' enable signal.(data direction)
|
||||||
|
-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'.
|
||||||
|
--
|
||||||
|
-- There is a mark of "--AS" in all the change points.
|
||||||
|
--
|
||||||
|
------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
--
|
||||||
|
-- Z80 compatible microprocessor core, asynchronous top level
|
||||||
|
--
|
||||||
|
-- Version : 0247
|
||||||
|
--
|
||||||
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
--
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
||||||
|
-- Please report bugs to the author, but before you do so, please
|
||||||
|
-- make sure that this is not a derivative work and that
|
||||||
|
-- you have the latest version of this file.
|
||||||
|
--
|
||||||
|
-- The latest version of this file can be found at:
|
||||||
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
|
--
|
||||||
|
-- Limitations :
|
||||||
|
--
|
||||||
|
-- File history :
|
||||||
|
--
|
||||||
|
-- 0208 : First complete release
|
||||||
|
--
|
||||||
|
-- 0211 : Fixed interrupt cycle
|
||||||
|
--
|
||||||
|
-- 0235 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0238 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0240 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0242 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0247 : Fixed bus req/ack cycle
|
||||||
|
--
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
use IEEE.numeric_std.all;
|
||||||
|
use work.T80_Pack.all;
|
||||||
|
|
||||||
|
entity T80as is
|
||||||
|
generic(
|
||||||
|
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
RESET_n : in std_logic;
|
||||||
|
CLK_n : in std_logic;
|
||||||
|
WAIT_n : in std_logic;
|
||||||
|
INT_n : in std_logic;
|
||||||
|
NMI_n : in std_logic;
|
||||||
|
BUSRQ_n : in std_logic;
|
||||||
|
M1_n : out std_logic;
|
||||||
|
MREQ_n : out std_logic;
|
||||||
|
IORQ_n : out std_logic;
|
||||||
|
RD_n : out std_logic;
|
||||||
|
WR_n : out std_logic;
|
||||||
|
RFSH_n : out std_logic;
|
||||||
|
HALT_n : out std_logic;
|
||||||
|
BUSAK_n : out std_logic;
|
||||||
|
A : out std_logic_vector(15 downto 0);
|
||||||
|
--AS-- D : inout std_logic_vector(7 downto 0)
|
||||||
|
--AS>>
|
||||||
|
DI : in std_logic_vector(7 downto 0);
|
||||||
|
DO : out std_logic_vector(7 downto 0);
|
||||||
|
DOE : out std_logic
|
||||||
|
--<<AS
|
||||||
|
);
|
||||||
|
end T80as;
|
||||||
|
|
||||||
|
architecture rtl of T80as is
|
||||||
|
|
||||||
|
signal CEN : std_logic;
|
||||||
|
signal Reset_s : std_logic;
|
||||||
|
signal IntCycle_n : std_logic;
|
||||||
|
signal IORQ : std_logic;
|
||||||
|
signal NoRead : std_logic;
|
||||||
|
signal Write : std_logic;
|
||||||
|
signal MREQ : std_logic;
|
||||||
|
signal MReq_Inhibit : std_logic;
|
||||||
|
signal Req_Inhibit : std_logic;
|
||||||
|
signal RD : std_logic;
|
||||||
|
signal MREQ_n_i : std_logic;
|
||||||
|
signal IORQ_n_i : std_logic;
|
||||||
|
signal RD_n_i : std_logic;
|
||||||
|
signal WR_n_i : std_logic;
|
||||||
|
signal RFSH_n_i : std_logic;
|
||||||
|
signal BUSAK_n_i : std_logic;
|
||||||
|
signal A_i : std_logic_vector(15 downto 0);
|
||||||
|
--AS-- signal DO : std_logic_vector(7 downto 0);
|
||||||
|
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
|
||||||
|
signal Wait_s : std_logic;
|
||||||
|
signal MCycle : std_logic_vector(2 downto 0);
|
||||||
|
signal TState : std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
CEN <= '1';
|
||||||
|
|
||||||
|
BUSAK_n <= BUSAK_n_i;
|
||||||
|
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
|
||||||
|
RD_n_i <= not RD or Req_Inhibit;
|
||||||
|
|
||||||
|
--AS-- MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
--AS-- IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
--AS-- RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
--AS-- WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
--AS-- RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
|
||||||
|
--AS-- A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
|
||||||
|
--AS-- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
|
||||||
|
--AS>>
|
||||||
|
MREQ_n <= MREQ_n_i;
|
||||||
|
IORQ_n <= IORQ_n_i;
|
||||||
|
RD_n <= RD_n_i;
|
||||||
|
WR_n <= WR_n_i;
|
||||||
|
RFSH_n <= RFSH_n_i;
|
||||||
|
A <= A_i;
|
||||||
|
DOE <= Write when BUSAK_n_i = '1' else '0';
|
||||||
|
--<<AS
|
||||||
|
process (RESET_n, CLK_n)
|
||||||
|
begin
|
||||||
|
if RESET_n = '0' then
|
||||||
|
Reset_s <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
Reset_s <= '1';
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
u0 : T80
|
||||||
|
generic map(
|
||||||
|
Mode => Mode,
|
||||||
|
IOWait => 1)
|
||||||
|
port map(
|
||||||
|
CEN => CEN,
|
||||||
|
M1_n => M1_n,
|
||||||
|
IORQ => IORQ,
|
||||||
|
NoRead => NoRead,
|
||||||
|
Write => Write,
|
||||||
|
RFSH_n => RFSH_n_i,
|
||||||
|
HALT_n => HALT_n,
|
||||||
|
WAIT_n => Wait_s,
|
||||||
|
INT_n => INT_n,
|
||||||
|
NMI_n => NMI_n,
|
||||||
|
RESET_n => Reset_s,
|
||||||
|
BUSRQ_n => BUSRQ_n,
|
||||||
|
BUSAK_n => BUSAK_n_i,
|
||||||
|
CLK_n => CLK_n,
|
||||||
|
A => A_i,
|
||||||
|
-- DInst => D,
|
||||||
|
DInst => DI,
|
||||||
|
DI => DI_Reg,
|
||||||
|
DO => DO,
|
||||||
|
MC => MCycle,
|
||||||
|
TS => TState,
|
||||||
|
IntCycle_n => IntCycle_n);
|
||||||
|
|
||||||
|
process (CLK_n)
|
||||||
|
begin
|
||||||
|
if CLK_n'event and CLK_n = '0' then
|
||||||
|
Wait_s <= WAIT_n;
|
||||||
|
if TState = "011" and BUSAK_n_i = '1' then
|
||||||
|
--AS-- DI_Reg <= to_x01(D);
|
||||||
|
--AS>>
|
||||||
|
DI_Reg <= to_x01(DI);
|
||||||
|
--<<AS
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process (Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
WR_n_i <= '1';
|
||||||
|
-- 2004.10.18 modification
|
||||||
|
-- elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
WR_n_i <= '1';
|
||||||
|
-- if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
|
||||||
|
if TState = "010" then
|
||||||
|
WR_n_i <= not Write;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process (Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
Req_Inhibit <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
if MCycle = "001" and TState = "010" then
|
||||||
|
Req_Inhibit <= '1';
|
||||||
|
else
|
||||||
|
Req_Inhibit <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process (Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
MReq_Inhibit <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
if MCycle = "001" and TState = "010" then
|
||||||
|
MReq_Inhibit <= '1';
|
||||||
|
else
|
||||||
|
MReq_Inhibit <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
process(Reset_s,CLK_n)
|
||||||
|
begin
|
||||||
|
if Reset_s = '0' then
|
||||||
|
RD <= '0';
|
||||||
|
IORQ_n_i <= '1';
|
||||||
|
MREQ <= '0';
|
||||||
|
elsif CLK_n'event and CLK_n = '0' then
|
||||||
|
|
||||||
|
if MCycle = "001" then
|
||||||
|
if TState = "001" then
|
||||||
|
RD <= IntCycle_n;
|
||||||
|
MREQ <= IntCycle_n;
|
||||||
|
IORQ_n_i <= IntCycle_n;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
RD <= '0';
|
||||||
|
IORQ_n_i <= '1';
|
||||||
|
MREQ <= '1';
|
||||||
|
end if;
|
||||||
|
if TState = "100" then
|
||||||
|
MREQ <= '0';
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if TState = "001" and NoRead = '0' then
|
||||||
|
RD <= not Write;
|
||||||
|
IORQ_n_i <= not IORQ;
|
||||||
|
MREQ <= not IORQ;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
RD <= '0';
|
||||||
|
IORQ_n_i <= '1';
|
||||||
|
MREQ <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end;
|
@ -1,212 +1,216 @@
|
|||||||
--
|
--
|
||||||
-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig)
|
-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig)
|
||||||
--
|
--
|
||||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
--
|
--
|
||||||
-- All rights reserved
|
-- All rights reserved
|
||||||
--
|
--
|
||||||
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
--
|
--
|
||||||
-- Redistributions of source code must retain the above copyright notice,
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
||||||
--
|
--
|
||||||
-- Redistributions in synthesized form must reproduce the above copyright
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
|
||||||
--
|
--
|
||||||
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
||||||
-- specific prior written permission.
|
-- specific prior written permission.
|
||||||
--
|
--
|
||||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
--
|
--
|
||||||
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
||||||
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
||||||
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
||||||
--
|
--
|
||||||
-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
||||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
--
|
--
|
||||||
-- File history :
|
-- File history :
|
||||||
--
|
--
|
||||||
-- v1.0: convert to preudo-asynchronous model with original Z80 timings.
|
-- v1.0: convert to preudo-asynchronous model with original Z80 timings.
|
||||||
--
|
--
|
||||||
-- v2.0: rewritten for more precise timings.
|
-- v2.0: rewritten for more precise timings.
|
||||||
-- support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2.
|
-- support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2.
|
||||||
--
|
--
|
||||||
-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
|
-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
|
||||||
--
|
--
|
||||||
-- v2.2: Interrupt acknowledge cycle has been corrected
|
-- v2.2: Interrupt acknowledge cycle has been corrected
|
||||||
-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
|
-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
|
||||||
--
|
--
|
||||||
-- v2.3: Output last used Address during non-bus MCycle seems more correct.
|
-- v2.3: Output last used Address during non-bus MCycle seems more correct.
|
||||||
--
|
--
|
||||||
|
-- v2.4: Use the fixed WAIT_n in T80.vhd
|
||||||
library IEEE;
|
--
|
||||||
use IEEE.std_logic_1164.all;
|
|
||||||
use IEEE.numeric_std.all;
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
entity T80pa is
|
use IEEE.numeric_std.all;
|
||||||
generic(
|
use work.T80_Pack.all;
|
||||||
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
|
||||||
);
|
entity T80pa is
|
||||||
port(
|
generic(
|
||||||
RESET_n : in std_logic;
|
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||||
CLK : in std_logic;
|
);
|
||||||
CEN_p : in std_logic := '1';
|
port(
|
||||||
CEN_n : in std_logic := '1';
|
RESET_n : in std_logic;
|
||||||
WAIT_n : in std_logic := '1';
|
CLK : in std_logic;
|
||||||
INT_n : in std_logic := '1';
|
CEN_p : in std_logic := '1';
|
||||||
NMI_n : in std_logic := '1';
|
CEN_n : in std_logic := '1';
|
||||||
BUSRQ_n : in std_logic := '1';
|
WAIT_n : in std_logic := '1';
|
||||||
M1_n : out std_logic;
|
INT_n : in std_logic := '1';
|
||||||
MREQ_n : out std_logic;
|
NMI_n : in std_logic := '1';
|
||||||
IORQ_n : out std_logic;
|
BUSRQ_n : in std_logic := '1';
|
||||||
RD_n : out std_logic;
|
M1_n : out std_logic;
|
||||||
WR_n : out std_logic;
|
MREQ_n : out std_logic;
|
||||||
RFSH_n : out std_logic;
|
IORQ_n : out std_logic;
|
||||||
HALT_n : out std_logic;
|
RD_n : out std_logic;
|
||||||
BUSAK_n : out std_logic;
|
WR_n : out std_logic;
|
||||||
OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
|
RFSH_n : out std_logic;
|
||||||
A : out std_logic_vector(15 downto 0);
|
HALT_n : out std_logic;
|
||||||
DI : in std_logic_vector(7 downto 0);
|
BUSAK_n : out std_logic;
|
||||||
DO : out std_logic_vector(7 downto 0);
|
OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
|
||||||
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
|
A : out std_logic_vector(15 downto 0);
|
||||||
);
|
DI : in std_logic_vector(7 downto 0);
|
||||||
end T80pa;
|
DO : out std_logic_vector(7 downto 0);
|
||||||
|
R800_mode : in std_logic := '0';
|
||||||
architecture rtl of T80pa is
|
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
|
||||||
|
DIRSet : in std_logic := '0';
|
||||||
signal IntCycle_n : std_logic;
|
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
|
||||||
signal IntCycleD_n : std_logic_vector(1 downto 0);
|
);
|
||||||
signal IORQ : std_logic;
|
end T80pa;
|
||||||
signal NoRead : std_logic;
|
|
||||||
signal Write : std_logic;
|
architecture rtl of T80pa is
|
||||||
signal BUSAK : std_logic;
|
|
||||||
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
|
signal IntCycle_n : std_logic;
|
||||||
signal MCycle : std_logic_vector(2 downto 0);
|
signal IntCycleD_n : std_logic_vector(1 downto 0);
|
||||||
signal TState : std_logic_vector(2 downto 0);
|
signal IORQ : std_logic;
|
||||||
signal CEN_pol : std_logic;
|
signal NoRead : std_logic;
|
||||||
signal A_int : std_logic_vector(15 downto 0);
|
signal Write : std_logic;
|
||||||
signal A_last : std_logic_vector(15 downto 0);
|
signal BUSAK : std_logic;
|
||||||
|
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
|
||||||
begin
|
signal MCycle : std_logic_vector(2 downto 0);
|
||||||
|
signal TState : std_logic_vector(2 downto 0);
|
||||||
A <= A_int when NoRead = '0' or Write = '1' else A_last;
|
signal CEN_pol : std_logic;
|
||||||
|
signal CEN : std_logic;
|
||||||
BUSAK_n <= BUSAK;
|
signal Wait_s : std_logic;
|
||||||
|
begin
|
||||||
u0 : work.T80
|
|
||||||
generic map(
|
CEN <= CEN_p and not CEN_pol;
|
||||||
Mode => Mode,
|
BUSAK_n <= BUSAK;
|
||||||
IOWait => 1
|
|
||||||
)
|
u0 : T80
|
||||||
port map(
|
generic map(
|
||||||
CEN => CEN_p and not CEN_pol,
|
Mode => Mode,
|
||||||
M1_n => M1_n,
|
IOWait => 1
|
||||||
IORQ => IORQ,
|
)
|
||||||
NoRead => NoRead,
|
port map(
|
||||||
Write => Write,
|
CEN => CEN,
|
||||||
RFSH_n => RFSH_n,
|
M1_n => M1_n,
|
||||||
HALT_n => HALT_n,
|
IORQ => IORQ,
|
||||||
WAIT_n => '1',
|
NoRead => NoRead,
|
||||||
INT_n => INT_n,
|
Write => Write,
|
||||||
NMI_n => NMI_n,
|
RFSH_n => RFSH_n,
|
||||||
RESET_n => RESET_n,
|
HALT_n => HALT_n,
|
||||||
BUSRQ_n => BUSRQ_n,
|
WAIT_n => Wait_s,
|
||||||
BUSAK_n => BUSAK,
|
INT_n => INT_n,
|
||||||
CLK_n => CLK,
|
NMI_n => NMI_n,
|
||||||
A => A_int,
|
RESET_n => RESET_n,
|
||||||
DInst => DI, -- valid at beginning of T3
|
BUSRQ_n => BUSRQ_n,
|
||||||
DI => DI_Reg, -- latched at middle of T3
|
BUSAK_n => BUSAK,
|
||||||
DO => DO,
|
CLK_n => CLK,
|
||||||
REG => REG,
|
A => A,
|
||||||
MC => MCycle,
|
DInst => DI, -- valid at beginning of T3
|
||||||
TS => TState,
|
DI => DI_Reg, -- latched at middle of T3
|
||||||
OUT0 => OUT0,
|
DO => DO,
|
||||||
IntCycle_n => IntCycle_n
|
REG => REG,
|
||||||
);
|
MC => MCycle,
|
||||||
|
TS => TState,
|
||||||
process(CLK)
|
OUT0 => OUT0,
|
||||||
begin
|
R800_mode => R800_mode,
|
||||||
if rising_edge(CLK) then
|
IntCycle_n => IntCycle_n,
|
||||||
if RESET_n = '0' then
|
DIRSet => DIRSet,
|
||||||
WR_n <= '1';
|
DIR => DIR
|
||||||
RD_n <= '1';
|
);
|
||||||
IORQ_n <= '1';
|
|
||||||
MREQ_n <= '1';
|
process(CLK)
|
||||||
DI_Reg <= "00000000";
|
begin
|
||||||
CEN_pol <= '0';
|
if rising_edge(CLK) then
|
||||||
elsif CEN_p = '1' and CEN_pol = '0' then
|
if RESET_n = '0' then
|
||||||
CEN_pol <= '1';
|
WR_n <= '1';
|
||||||
if MCycle = "001" then
|
RD_n <= '1';
|
||||||
if TState = "010" then
|
IORQ_n <= '1';
|
||||||
IORQ_n <= '1';
|
MREQ_n <= '1';
|
||||||
MREQ_n <= '1';
|
DI_Reg <= "00000000";
|
||||||
RD_n <= '1';
|
CEN_pol <= '0';
|
||||||
end if;
|
elsif CEN_p = '1' and CEN_pol = '0' then
|
||||||
else
|
CEN_pol <= '1';
|
||||||
if TState = "001" and IORQ = '1' then
|
if WAIT_s = '1' or TState /= "010" then
|
||||||
WR_n <= not Write;
|
if MCycle = "001" then
|
||||||
RD_n <= Write;
|
if TState = "010" then
|
||||||
IORQ_n <= '0';
|
IORQ_n <= '1';
|
||||||
end if;
|
MREQ_n <= '1';
|
||||||
end if;
|
RD_n <= '1';
|
||||||
elsif CEN_n = '1' and CEN_pol = '1' then
|
end if;
|
||||||
if TState = "010" then
|
else
|
||||||
CEN_pol <= not WAIT_n;
|
if TState = "001" and IORQ = '1' then
|
||||||
else
|
WR_n <= not Write;
|
||||||
CEN_pol <= '0';
|
RD_n <= Write;
|
||||||
end if;
|
IORQ_n <= '0';
|
||||||
if TState = "011" and BUSAK = '1' then
|
end if;
|
||||||
DI_Reg <= DI;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
if MCycle = "001" then
|
elsif CEN_n = '1' and CEN_pol = '1' then
|
||||||
if TState = "001" then
|
Wait_s <= Wait_n;
|
||||||
IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
|
CEN_pol <= '0';
|
||||||
RD_n <= not IntCycle_n;
|
if TState = "011" and BUSAK = '1' then
|
||||||
MREQ_n <= not IntCycle_n;
|
DI_Reg <= DI;
|
||||||
IORQ_n <= IntCycleD_n(1);
|
end if;
|
||||||
A_last <= A_int;
|
if MCycle = "001" then
|
||||||
end if;
|
if TState = "001" then
|
||||||
if TState = "011" then
|
IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
|
||||||
IntCycleD_n <= "11";
|
RD_n <= not IntCycle_n;
|
||||||
RD_n <= '1';
|
MREQ_n <= not IntCycle_n;
|
||||||
MREQ_n <= '0';
|
IORQ_n <= IntCycleD_n(1);
|
||||||
end if;
|
end if;
|
||||||
if TState = "100" then
|
if TState = "011" then
|
||||||
MREQ_n <= '1';
|
IntCycleD_n <= "11";
|
||||||
end if;
|
RD_n <= '1';
|
||||||
else
|
MREQ_n <= '0';
|
||||||
if NoRead = '0' and IORQ = '0' then
|
end if;
|
||||||
if TState = "001" then
|
if TState = "100" then
|
||||||
RD_n <= Write;
|
MREQ_n <= '1';
|
||||||
MREQ_n <= '0';
|
end if;
|
||||||
A_last <= A_int;
|
else
|
||||||
end if;
|
if NoRead = '0' and IORQ = '0' then
|
||||||
end if;
|
if TState = "001" then
|
||||||
if TState = "010" then
|
RD_n <= Write;
|
||||||
WR_n <= not Write;
|
MREQ_n <= '0';
|
||||||
end if;
|
end if;
|
||||||
if TState = "011" then
|
end if;
|
||||||
WR_n <= '1';
|
if TState = "010" then
|
||||||
RD_n <= '1';
|
WR_n <= not Write;
|
||||||
IORQ_n <= '1';
|
end if;
|
||||||
MREQ_n <= '1';
|
if TState = "011" then
|
||||||
end if;
|
WR_n <= '1';
|
||||||
end if;
|
RD_n <= '1';
|
||||||
end if;
|
IORQ_n <= '1';
|
||||||
end if;
|
MREQ_n <= '1';
|
||||||
end process;
|
end if;
|
||||||
end;
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
end;
|
||||||
|
@ -69,6 +69,7 @@ library IEEE;
|
|||||||
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
||||||
use IEEE.numeric_std.all;
|
use IEEE.numeric_std.all;
|
||||||
use IEEE.STD_LOGIC_UNSIGNED.all;
|
use IEEE.STD_LOGIC_UNSIGNED.all;
|
||||||
|
use work.T80_Pack.all;
|
||||||
|
|
||||||
entity T80s is
|
entity T80s is
|
||||||
generic(
|
generic(
|
||||||
@ -111,7 +112,7 @@ architecture rtl of T80s is
|
|||||||
|
|
||||||
begin
|
begin
|
||||||
|
|
||||||
u0 : work.T80
|
u0 : T80
|
||||||
generic map(
|
generic map(
|
||||||
Mode => Mode,
|
Mode => Mode,
|
||||||
IOWait => IOWait)
|
IOWait => IOWait)
|
||||||
|
192
rtl/T80/T80se.vhd
Normal file
192
rtl/T80/T80se.vhd
Normal file
@ -0,0 +1,192 @@
|
|||||||
|
-- ****
|
||||||
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
|
--
|
||||||
|
--
|
||||||
|
-- Ver 300 started tidyup
|
||||||
|
-- MikeJ March 2005
|
||||||
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
--
|
||||||
|
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||||
|
-- Different timing than the original z80
|
||||||
|
-- Inputs needs to be synchronous and outputs may glitch
|
||||||
|
--
|
||||||
|
-- Version : 0240
|
||||||
|
--
|
||||||
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
--
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
||||||
|
-- Please report bugs to the author, but before you do so, please
|
||||||
|
-- make sure that this is not a derivative work and that
|
||||||
|
-- you have the latest version of this file.
|
||||||
|
--
|
||||||
|
-- The latest version of this file can be found at:
|
||||||
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
|
--
|
||||||
|
-- Limitations :
|
||||||
|
--
|
||||||
|
-- File history :
|
||||||
|
--
|
||||||
|
-- 0235 : First release
|
||||||
|
--
|
||||||
|
-- 0236 : Added T2Write generic
|
||||||
|
--
|
||||||
|
-- 0237 : Fixed T2Write with wait state
|
||||||
|
--
|
||||||
|
-- 0238 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0240 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0242 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
use IEEE.numeric_std.all;
|
||||||
|
use work.T80_Pack.all;
|
||||||
|
|
||||||
|
entity T80se is
|
||||||
|
generic(
|
||||||
|
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||||
|
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
||||||
|
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||||
|
);
|
||||||
|
port(
|
||||||
|
RESET_n : in std_logic;
|
||||||
|
CLK_n : in std_logic;
|
||||||
|
CLKEN : in std_logic;
|
||||||
|
WAIT_n : in std_logic;
|
||||||
|
INT_n : in std_logic;
|
||||||
|
NMI_n : in std_logic;
|
||||||
|
BUSRQ_n : in std_logic;
|
||||||
|
M1_n : out std_logic;
|
||||||
|
MREQ_n : out std_logic;
|
||||||
|
IORQ_n : out std_logic;
|
||||||
|
RD_n : out std_logic;
|
||||||
|
WR_n : out std_logic;
|
||||||
|
RFSH_n : out std_logic;
|
||||||
|
HALT_n : out std_logic;
|
||||||
|
BUSAK_n : out std_logic;
|
||||||
|
A : out std_logic_vector(15 downto 0);
|
||||||
|
DI : in std_logic_vector(7 downto 0);
|
||||||
|
DO : out std_logic_vector(7 downto 0)
|
||||||
|
);
|
||||||
|
end T80se;
|
||||||
|
|
||||||
|
architecture rtl of T80se is
|
||||||
|
|
||||||
|
signal IntCycle_n : std_logic;
|
||||||
|
signal NoRead : std_logic;
|
||||||
|
signal Write : std_logic;
|
||||||
|
signal IORQ : std_logic;
|
||||||
|
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||||
|
signal MCycle : std_logic_vector(2 downto 0);
|
||||||
|
signal TState : std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
u0 : T80
|
||||||
|
generic map(
|
||||||
|
Mode => Mode,
|
||||||
|
IOWait => IOWait)
|
||||||
|
port map(
|
||||||
|
CEN => CLKEN,
|
||||||
|
M1_n => M1_n,
|
||||||
|
IORQ => IORQ,
|
||||||
|
NoRead => NoRead,
|
||||||
|
Write => Write,
|
||||||
|
RFSH_n => RFSH_n,
|
||||||
|
HALT_n => HALT_n,
|
||||||
|
WAIT_n => Wait_n,
|
||||||
|
INT_n => INT_n,
|
||||||
|
NMI_n => NMI_n,
|
||||||
|
RESET_n => RESET_n,
|
||||||
|
BUSRQ_n => BUSRQ_n,
|
||||||
|
BUSAK_n => BUSAK_n,
|
||||||
|
CLK_n => CLK_n,
|
||||||
|
A => A,
|
||||||
|
DInst => DI,
|
||||||
|
DI => DI_Reg,
|
||||||
|
DO => DO,
|
||||||
|
MC => MCycle,
|
||||||
|
TS => TState,
|
||||||
|
IntCycle_n => IntCycle_n);
|
||||||
|
|
||||||
|
process (RESET_n, CLK_n)
|
||||||
|
begin
|
||||||
|
if RESET_n = '0' then
|
||||||
|
RD_n <= '1';
|
||||||
|
WR_n <= '1';
|
||||||
|
IORQ_n <= '1';
|
||||||
|
MREQ_n <= '1';
|
||||||
|
DI_Reg <= "00000000";
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
if CLKEN = '1' then
|
||||||
|
RD_n <= '1';
|
||||||
|
WR_n <= '1';
|
||||||
|
IORQ_n <= '1';
|
||||||
|
MREQ_n <= '1';
|
||||||
|
if MCycle = "001" then
|
||||||
|
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||||
|
RD_n <= not IntCycle_n;
|
||||||
|
MREQ_n <= not IntCycle_n;
|
||||||
|
IORQ_n <= IntCycle_n;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
MREQ_n <= '0';
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
|
||||||
|
RD_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
if T2Write = 0 then
|
||||||
|
if TState = "010" and Write = '1' then
|
||||||
|
WR_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
|
||||||
|
WR_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if TState = "010" and Wait_n = '1' then
|
||||||
|
DI_Reg <= DI;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end;
|
179
rtl/T80/T80sed.vhd
Normal file
179
rtl/T80/T80sed.vhd
Normal file
@ -0,0 +1,179 @@
|
|||||||
|
-- ****
|
||||||
|
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||||
|
--
|
||||||
|
--
|
||||||
|
-- Ver 300 started tidyup
|
||||||
|
-- MikeJ March 2005
|
||||||
|
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||||
|
--
|
||||||
|
-- ****
|
||||||
|
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
|
||||||
|
--
|
||||||
|
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||||
|
-- Different timing than the original z80
|
||||||
|
-- Inputs needs to be synchronous and outputs may glitch
|
||||||
|
--
|
||||||
|
-- Version : 0238
|
||||||
|
--
|
||||||
|
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||||
|
--
|
||||||
|
-- All rights reserved
|
||||||
|
--
|
||||||
|
-- Redistribution and use in source and synthezised forms, with or without
|
||||||
|
-- modification, are permitted provided that the following conditions are met:
|
||||||
|
--
|
||||||
|
-- Redistributions of source code must retain the above copyright notice,
|
||||||
|
-- this list of conditions and the following disclaimer.
|
||||||
|
--
|
||||||
|
-- Redistributions in synthesized form must reproduce the above copyright
|
||||||
|
-- notice, this list of conditions and the following disclaimer in the
|
||||||
|
-- documentation and/or other materials provided with the distribution.
|
||||||
|
--
|
||||||
|
-- Neither the name of the author nor the names of other contributors may
|
||||||
|
-- be used to endorse or promote products derived from this software without
|
||||||
|
-- specific prior written permission.
|
||||||
|
--
|
||||||
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||||
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||||
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||||
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
-- POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
--
|
||||||
|
-- Please report bugs to the author, but before you do so, please
|
||||||
|
-- make sure that this is not a derivative work and that
|
||||||
|
-- you have the latest version of this file.
|
||||||
|
--
|
||||||
|
-- The latest version of this file can be found at:
|
||||||
|
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||||
|
--
|
||||||
|
-- Limitations :
|
||||||
|
--
|
||||||
|
-- File history :
|
||||||
|
--
|
||||||
|
-- 0235 : First release
|
||||||
|
--
|
||||||
|
-- 0236 : Added T2Write generic
|
||||||
|
--
|
||||||
|
-- 0237 : Fixed T2Write with wait state
|
||||||
|
--
|
||||||
|
-- 0238 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
-- 0242 : Updated for T80 interface change
|
||||||
|
--
|
||||||
|
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
use IEEE.numeric_std.all;
|
||||||
|
use work.T80_Pack.all;
|
||||||
|
|
||||||
|
entity T80sed is
|
||||||
|
port(
|
||||||
|
RESET_n : in std_logic;
|
||||||
|
CLK_n : in std_logic;
|
||||||
|
CLKEN : in std_logic;
|
||||||
|
WAIT_n : in std_logic;
|
||||||
|
INT_n : in std_logic;
|
||||||
|
NMI_n : in std_logic;
|
||||||
|
BUSRQ_n : in std_logic;
|
||||||
|
M1_n : out std_logic;
|
||||||
|
MREQ_n : out std_logic;
|
||||||
|
IORQ_n : out std_logic;
|
||||||
|
RD_n : out std_logic;
|
||||||
|
WR_n : out std_logic;
|
||||||
|
RFSH_n : out std_logic;
|
||||||
|
HALT_n : out std_logic;
|
||||||
|
BUSAK_n : out std_logic;
|
||||||
|
A : out std_logic_vector(15 downto 0);
|
||||||
|
DI : in std_logic_vector(7 downto 0);
|
||||||
|
DO : out std_logic_vector(7 downto 0)
|
||||||
|
);
|
||||||
|
end T80sed;
|
||||||
|
|
||||||
|
architecture rtl of T80sed is
|
||||||
|
|
||||||
|
signal IntCycle_n : std_logic;
|
||||||
|
signal NoRead : std_logic;
|
||||||
|
signal Write : std_logic;
|
||||||
|
signal IORQ : std_logic;
|
||||||
|
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||||
|
signal MCycle : std_logic_vector(2 downto 0);
|
||||||
|
signal TState : std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
|
begin
|
||||||
|
|
||||||
|
u0 : T80
|
||||||
|
generic map(
|
||||||
|
Mode => 0,
|
||||||
|
IOWait => 1)
|
||||||
|
port map(
|
||||||
|
CEN => CLKEN,
|
||||||
|
M1_n => M1_n,
|
||||||
|
IORQ => IORQ,
|
||||||
|
NoRead => NoRead,
|
||||||
|
Write => Write,
|
||||||
|
RFSH_n => RFSH_n,
|
||||||
|
HALT_n => HALT_n,
|
||||||
|
WAIT_n => Wait_n,
|
||||||
|
INT_n => INT_n,
|
||||||
|
NMI_n => NMI_n,
|
||||||
|
RESET_n => RESET_n,
|
||||||
|
BUSRQ_n => BUSRQ_n,
|
||||||
|
BUSAK_n => BUSAK_n,
|
||||||
|
CLK_n => CLK_n,
|
||||||
|
A => A,
|
||||||
|
DInst => DI,
|
||||||
|
DI => DI_Reg,
|
||||||
|
DO => DO,
|
||||||
|
MC => MCycle,
|
||||||
|
TS => TState,
|
||||||
|
IntCycle_n => IntCycle_n);
|
||||||
|
|
||||||
|
process (RESET_n, CLK_n)
|
||||||
|
begin
|
||||||
|
if RESET_n = '0' then
|
||||||
|
RD_n <= '1';
|
||||||
|
WR_n <= '1';
|
||||||
|
IORQ_n <= '1';
|
||||||
|
MREQ_n <= '1';
|
||||||
|
DI_Reg <= "00000000";
|
||||||
|
elsif CLK_n'event and CLK_n = '1' then
|
||||||
|
if CLKEN = '1' then
|
||||||
|
RD_n <= '1';
|
||||||
|
WR_n <= '1';
|
||||||
|
IORQ_n <= '1';
|
||||||
|
MREQ_n <= '1';
|
||||||
|
if MCycle = "001" then
|
||||||
|
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||||
|
RD_n <= not IntCycle_n;
|
||||||
|
MREQ_n <= not IntCycle_n;
|
||||||
|
IORQ_n <= IntCycle_n;
|
||||||
|
end if;
|
||||||
|
if TState = "011" then
|
||||||
|
MREQ_n <= '0';
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
|
||||||
|
RD_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
if ((TState = "001") or (TState = "010")) and Write = '1' then
|
||||||
|
WR_n <= '0';
|
||||||
|
IORQ_n <= not IORQ;
|
||||||
|
MREQ_n <= IORQ;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
if TState = "010" and Wait_n = '1' then
|
||||||
|
DI_Reg <= DI;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
end;
|
Reference in New Issue
Block a user