mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
Remove loader, embed the BIOS into core.
This commit is contained in:
sorgelig
@ -265,7 +265,6 @@ tsconf tsconf
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.SD_CLK(sdclk),
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.SD_CLK(sdclk),
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.SD_CS_N(sdss),
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.SD_CS_N(sdss),
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.GS_ENA(1),
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.GS_ADDR(gs_mem_addr),
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.GS_ADDR(gs_mem_addr),
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.GS_DI(gs_mem_din),
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.GS_DI(gs_mem_din),
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.GS_DO(gs_mem_dout | gs_mem_mask),
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.GS_DO(gs_mem_dout | gs_mem_mask),
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Binary file not shown.
BIN
src/loader_fat32/.DS_Store
vendored
BIN
src/loader_fat32/.DS_Store
vendored
Binary file not shown.
@ -1,318 +0,0 @@
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#!/usr/bin/env python
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"""
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File: bin2hex.py
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Converts a binary file into intel hex format. For usage try $bin2hex.py -h
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License
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The MIT License
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this hardware, software, and associated documentation files (the
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"Product"), to deal in the Product without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Product, and to permit
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persons to whom the Product is furnished to do so, subject to the
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following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Product.
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THE PRODUCT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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PRODUCT OR THE USE OR OTHER DEALINGS IN THE PRODUCT.
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"""
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import sys
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import os
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import errno
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import optparse
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import struct
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HEX_TYPE_DATA = 0
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HEX_TYPE_EOF = 1
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HEX_TYPE_EXT_SEG_ADDRESS = 2
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HEX_TYPE_START_SEG_ADDRESS = 3
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HEX_TYPE_EXT_LINEAR_ADDRESS = 4
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HEX_TYPE_START_LINEAR_ADDRESS = 5
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HEX_ALLOWED_ADDRESS_TYPES ={
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0:(1<<16)-1,
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2:(1<<20)-1,
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4:(1<<32)-1,
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}
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class HexRecord:
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def __init__(self, type, data, checksum = None, address = 0):
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self.__type = type
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self.__data = data
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self.__length = len(data)
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self.__address = address
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self.__checksum = self.__length + (address >> 8) + (address & 0xFF) + type
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for b in data:
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self.__checksum += b
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self.__checksum = (~self.__checksum) + 1
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self.__checksum = self.__checksum & 0xFF
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if (checksum is not None) and (self.__checksum != checksum):
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raise Exception("Error: Checksum does not match. Calculated %02X. Given %02X." % (self.__checksum, checksum))
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def getType(self):
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return self.__type
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def getData(self):
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return self.__data
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def getAddress(self):
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return self.__address
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def getRecord(self):
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# return string representation of the record.
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recordstr = ":%02X%04X%02X%s%02X" % (self.__length,
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self.__address,
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self.__type,
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"".join(["%02X" % b for b in self.__data]),
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self.__checksum)
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return recordstr
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def write(self, stream=sys.stdout):
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# write the record to stream
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stream.write(":%02X%04X%02X" % (self.__length, self.__address, self.__type))
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for b in self.__data:
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stream.write("%02X" % b)
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stream.write("%02X\n" % self.__checksum)
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def readHexFile(stream):
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records = []
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lineNum = 0
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for line in stream:
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lineNum += 1
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line = line.strip()
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if len(line) == 0:
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break
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if line[0] != ":":
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raise Exception("Error on line %d. Record does not start with ':' character. Starts with '%s'." % (lineNum, line[0]))
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byteCount = int(line[1:3], 16)
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address = int(line[3:7], 16)
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type = int(line[7:9], 16)
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if len(line) != (11 + 2*byteCount):
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raise Exception("Bad byteCount on line %d lineNum. Line length is %d chars, expected %d for byteCount %d." % (lineNum, len(line), 11+2*byteCount, byteCount))
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data = []
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for i in range(byteCount):
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hexPair = line[(9+2*i):(9+2*i+2)]
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byte = int(hexPair, 16)
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data.append(byte)
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checkSum = int(line[-2:], 16)
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records.append(HexRecord(type, data, checkSum, address))
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return records
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def generatehexfile(inputlist, hexsubsettype=4):
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''' From a sorted (by address) list of (address, binaryfilepath) tuples,
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produce a hex file string and return it. Assumes arguments are OK.
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Only hex subtype 4 is implemented.
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'''
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hexout = []
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if (hexsubsettype == 4):
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recordlength = 32
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elif (hexsubsettype == 2):
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recordlength = 16
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else:
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# not implemented
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return ''.join(hexout)
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# current address and segment address are carried between subfiles.
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curraddr = 0
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segaddr = 0
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for (addr, binfile) in inputlist:
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# open the file for processing
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with open(binfile, 'rb') as f:
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fsize = os.path.getsize(binfile)
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# set starting address.
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if addr >= (curraddr + segaddr):
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curraddr = addr - segaddr
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else:
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# shouldn't be out of order this way. error.
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raise UserWarning("Error: binfiles are out of order. Contact tool smith.")
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# work through the file generating & storing records as we go
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while f.tell() != fsize:
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# check if we need a new segment
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if (curraddr & 0xFFFF0000) != 0:
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# set new segaddr
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segaddr = (curraddr & 0xFFFF0000) + segaddr
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if hexsubsettype == 4:
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hexout.append(HexRecord(HEX_TYPE_EXT_LINEAR_ADDRESS, [(segaddr >> 24) & 0xFF, (segaddr >> 16) & 0xFF]).getRecord())
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elif hexsubsettype == 2:
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hexout.append(HexRecord(HEX_TYPE_EXT_SEG_ADDRESS, [(segaddr >> 12) & 0xFF, (segaddr >> 4) & 0xFF]).getRecord())
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else:
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raise UserWarning("Error: somehow hexsubsettype is broken, contact tool smith.")
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# advance address pointer
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curraddr = curraddr & 0x0000FFFF
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# read up to recordlength bytes from the file, don't bridge segment.
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if (curraddr + recordlength) > 0x10000:
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bytestoread = (curraddr + recordlength) - 0x10000;
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else:
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bytestoread = recordlength
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bindata = f.read(bytestoread)
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# bindata = struct.unpack('B'*len(bindata),bindata) # better to use ord actually
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bindata = map(ord, bindata)
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hexout.append(HexRecord(HEX_TYPE_DATA, bindata, address=curraddr).getRecord())
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curraddr += len(bindata)
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# add end of file record
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hexout.append(HexRecord(HEX_TYPE_EOF, []).getRecord())
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return hexout
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def checkhextypearg(option, opt, value, parser):
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# check hex type argument
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if value not in HEX_ALLOWED_ADDRESS_TYPES:
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raise optparse.OptionValueError ("Error: HEX format subset type %d not acceptable."%value)
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setattr(parser.values, option.dest, value)
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def commandline_split(option, opt, value, parser):
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# check the binary input
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binlist = value.split(',')
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if len(value.split(','))%2 != 0:
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raise optparse.OptionValueError("Error: each input binary must have a corresponding address")
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# convert to list of lists of (address, binfile)
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binlist = map(list, zip(*[iter(binlist)]*2))
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binlistout = []
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# make sure each argument in each pair is OK
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for [addr, binfile] in (binlist):
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# convert address to int. int() will raise any format errors
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rawaddr = addr
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if addr.find('0x') == 0:
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addr = int(addr, 16)
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else:
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addr = int(addr)
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if addr > 0xFFFFFFFF:
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raise optparse.OptionValueError("Error: address (%s, %s) exceeds 4gb."%(rawaddr, binfile))
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# ensure binfile path is ok, and abs it.
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if os.path.isfile(binfile):
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binfile = os.path.abspath(binfile)
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else:
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raise optparse.OptionValueError("Error: binfile path (%s, %s) is unacceptable"%(rawaddr, binfile))
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# save it to the output list as a tuple (unmodifiable after this), and
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# save the converted values to a list for examination later
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binlistout.append((addr, binfile))
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# now check if any file(size) + address will overlap another
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for i, binentry1 in enumerate(binlistout):
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for j, binentry2 in enumerate(binlistout):
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if (binentry1[0] < binentry2[0]) and (binentry1[0] + os.path.getsize(binentry1[1]) > binentry2[0]):
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raise optparse.OptionValueError("Error: binfile entry %s overlaps %s"%(str(binlist[i]), str(binlist[j])))
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# also check if addr + filesize is going to overflow 4gb limit
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if binentry1[0] + os.path.getsize(binentry1[1]) > (1<<32)-1:
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raise optparse.OptionValueError("Error: binfile entry %s exceeds 4gb limit"%(str(binlist[i])))
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# sort the output list (by address)
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binlistout.sort()
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setattr(parser.values, option.dest, binlistout)
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def process_command_line(argv=None):
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'''
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Return a 2-tuple: (settings object, args list).
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`argv` is a list of arguments, or `None` for ``sys.argv[1:]``.
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'''
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if argv is None:
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if len(sys.argv[1:]):
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argv = sys.argv[1:]
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else:
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argv = ['-h']
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||||||
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# initialize the parser object:
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parser = optparse.OptionParser(
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||||||
formatter=optparse.TitledHelpFormatter(width=70),
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add_help_option=None)
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|
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# define options here:
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parser.add_option('-r', '--format', dest='format', type="int",
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default=4, action='callback', callback=checkhextypearg,
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help='HEX format subtype. 0 is I8HEX, 2 is I16HEX, 4 is I32HEX. Default is %default. ONLY 2 AND 4 ACCEPTED RIGHT NOW.')
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parser.add_option('-b', '--binaries', dest='binaries', type='string',
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default=None, action='callback', callback=commandline_split,
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help='List of binary file inputs and start addresses. Addresses are either decimal or hex (must be prepended with 0x).', metavar='ADDRESS,FILE,ADDRESS,FILE,...')
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parser.add_option('-o', '--outfile', dest='outfile',
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||||||
default=None,
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||||||
help='Output file path, optional, defaults to first input binary file dot hex.', metavar='PATH')
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||||||
parser.add_option('-q', '--quiet',action="store_true", dest="quiet",
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default=False,
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||||||
help="Suppress non-critical output on stdout.")
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parser.add_option('-v', '--version',dest='version',
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||||||
action="store_true",
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default=False,
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||||||
help='Print version and exit.')
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parser.add_option('-h', '--help', action='help',
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help='Show this help message and exit.')
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|
||||||
|
|
||||||
settings, args = parser.parse_args(argv)
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|
||||||
|
|
||||||
# check number of arguments, verify values, etc.:
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|
||||||
if args:
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|
||||||
parser.error('error in arguments; '
|
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||||||
'"%s" ignored.' % (args,))
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||||||
|
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||||||
# further process settings & args if necessary
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||||||
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||||||
return settings, args
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||||||
|
|
||||||
if __name__ == "__main__":
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||||||
# set args and evaluate them
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||||||
# http://docs.python.org/2/library/optparse.html#optparse-extending-optparse
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||||||
settings,args = process_command_line()
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if settings.version:
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||||||
print "bin2hex.py %s"%("0.1")
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|
||||||
sys.exit(0)
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|
||||||
|
|
||||||
# make sure the selected hex record type can represent the largest address
|
|
||||||
maxaddress = HEX_ALLOWED_ADDRESS_TYPES[settings.format]
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||||||
for (addr, binfile) in settings.binaries:
|
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||||||
# don't check filesize, if it's good enough for gnu objcopy it's ok for us.
|
|
||||||
#if (addr + os.path.getsize(binfile)) > maxaddress:
|
|
||||||
#print "Error, address+binfile size 0x%0X is too large for format!"%(addr + os.path.getsize(binfile))
|
|
||||||
if addr > maxaddress:
|
|
||||||
print "Error, address size 0x%0X is too large for format!"%(addr)
|
|
||||||
exit(errno.EINVAL)
|
|
||||||
|
|
||||||
# check output file
|
|
||||||
try:
|
|
||||||
if settings.outfile is None:
|
|
||||||
# set output file based on first input file.
|
|
||||||
settings.outfile = os.path.splitext(settings.binaries[0][1])[0]+".hex"
|
|
||||||
# raise ValueError("Output file must be set!")
|
|
||||||
|
|
||||||
# now check the output file, make sure we can open it
|
|
||||||
with open(settings.outfile, 'w') as f:
|
|
||||||
pass
|
|
||||||
except Exception as inst:
|
|
||||||
print "Error with output file: %s"%inst
|
|
||||||
sys.exit(errno.EINVAL)
|
|
||||||
|
|
||||||
# now, produce the hex file from the input files and addresses
|
|
||||||
hexfiledata = generatehexfile(settings.binaries, settings.format)
|
|
||||||
|
|
||||||
# save it to the selected output file
|
|
||||||
with open(settings.outfile, 'w') as f:
|
|
||||||
f.write('\n'.join(hexfiledata))
|
|
||||||
f.write('\n') # trailing newline
|
|
||||||
|
|
||||||
@ -1,214 +0,0 @@
|
|||||||
DEVICE ZXSPECTRUM48
|
|
||||||
; -----------------------------------------------------------------------------
|
|
||||||
; LOADER(FAT32)
|
|
||||||
; -----------------------------------------------------------------------------
|
|
||||||
TX_Port EQU #F8EF
|
|
||||||
;-----CONST-----
|
|
||||||
TOTAL_PAGE EQU 31 ; 31(512kB ROM) //+ 2 (32kB) GS ROM
|
|
||||||
Start EQU #0000 ; BANK0 (ROM)
|
|
||||||
;================== LOADER EXEC CODE ==========================================
|
|
||||||
ORG Start ; Exec code - Bank0:
|
|
||||||
JP StartProg
|
|
||||||
;- LOADER ID -------------------------
|
|
||||||
;DB "LOADER(FAT32) V2.0/2014.09.10 | "
|
|
||||||
;DB "LOADED FILES:"
|
|
||||||
;- Name of ROMs files-----------------
|
|
||||||
FES1 DB #10 ;flag (#00 - file, #10 - dir)
|
|
||||||
DB "ROMS" ;DIR name
|
|
||||||
DB 0
|
|
||||||
;------
|
|
||||||
FES2 DB #00 ;flag (#00 - file, #10 - dir)
|
|
||||||
DB "ZXEVO.ROM" ;file name //"TEST128.ROM"
|
|
||||||
DB 0
|
|
||||||
;-------------------------------------
|
|
||||||
;------
|
|
||||||
;FES3 DB #00 ;flag (#00 - file, #10 - dir)
|
|
||||||
; DB "GS105A.ROM" ;file name - 32kB
|
|
||||||
; DB 0
|
|
||||||
;ORG #F0
|
|
||||||
;DB "Start Prog 0x100"
|
|
||||||
;=======================================================================
|
|
||||||
;ORG #100 ; Reserve 512byte
|
|
||||||
StartProg
|
|
||||||
DI ; DISABLE INT (PAGE2)
|
|
||||||
LD SP,PWA ; STACK_ADDR = BUFZZ+#4000; 0xC000-x
|
|
||||||
LD BC,SYC,A,DEFREQ:OUT(C), A ;SET DEFREQ:%00000010-14MHz
|
|
||||||
; <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> STACK - <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
||||||
;---PAGE3
|
|
||||||
LD B,PW3/256 : IN A,(C) ;READ PAGE3 //PW3:#13AF
|
|
||||||
LD (PGR3),A ;(PGR3) <- SAVE orig PAGE3
|
|
||||||
;---PAGE2
|
|
||||||
LD B,PW2/256 : IN A,(C) ;READ PAGE2 //PW2:#12AF
|
|
||||||
LD E,PG0: OUT (C),E ;SET PAGE2=0xF7
|
|
||||||
LD (PGR),A ;(PGR) <- SAVE orig PAGE2
|
|
||||||
;=======================================================
|
|
||||||
|
|
||||||
;=============== SD_LOADER========================================
|
|
||||||
SD_LOADER
|
|
||||||
;step_1 ======== INIT SD CARD ========
|
|
||||||
;LD A, #00
|
|
||||||
;CALL COM_TX
|
|
||||||
;-------
|
|
||||||
LD A, #00 ;STREAM: SD_INIT, HDD
|
|
||||||
CALL FAT_DRV
|
|
||||||
JR NZ,ERR ;INIT - FAILED
|
|
||||||
;step_2 ======= find DIR entry =======
|
|
||||||
LD HL,FES1
|
|
||||||
LD A, #01 ;find DIR entry
|
|
||||||
CALL FAT_DRV
|
|
||||||
JR NZ,ERR ;dir not found
|
|
||||||
;-------------------------------------
|
|
||||||
LD A, #02 ;SET CURR DIR - ACTIVE
|
|
||||||
CALL FAT_DRV
|
|
||||||
;step_3 ======= find File entry ====
|
|
||||||
LD HL,FES2
|
|
||||||
LD A, #01 ;find File entry
|
|
||||||
CALL FAT_DRV
|
|
||||||
JR NZ,ERR ;file not found
|
|
||||||
;step_4 ======= download data =======
|
|
||||||
LD A, #0 ;#0 - start page
|
|
||||||
CALL FAT32_LOADER ;
|
|
||||||
;step_5 ======= find File entry ======
|
|
||||||
;-------------------------------------
|
|
||||||
; LD HL,FES3
|
|
||||||
; LD A, #01 ;find File entry
|
|
||||||
; CALL FAT_DRV
|
|
||||||
; JR NZ,ERR ;file not found
|
|
||||||
;step_6 ======= download data ========
|
|
||||||
; LD A, 32 ;32 - start page DEC
|
|
||||||
; CALL FAT32_LOADER ;
|
|
||||||
;step_7 ======= INIT VS
|
|
||||||
; CALL VS_INIT
|
|
||||||
;----------------------
|
|
||||||
;LD A, #01
|
|
||||||
;CALL COM_TX
|
|
||||||
;----------------------
|
|
||||||
JP RESET_LOADER
|
|
||||||
;========================================================================================
|
|
||||||
FAT32_LOADER
|
|
||||||
;----------- Open 1st Page = ROM ========================================
|
|
||||||
;LD A, #0 ;download in page #0
|
|
||||||
LD (block_16kB_cnt), A ; RESTORE block_16kB_cnt
|
|
||||||
;CALL COM_TX
|
|
||||||
;-------------------------------
|
|
||||||
LD C, A ;page Number
|
|
||||||
LD DE,#0000 ;offset in PAGE:
|
|
||||||
LD B, 32 ;1 block-512Byte/32bloks-16kB
|
|
||||||
LD A, #3 ;code 3: LOAD512(TSFAT.ASM) c
|
|
||||||
CALL FAT_DRV ;return CDE - Address
|
|
||||||
;-------------------------------------------------------------------------------------
|
|
||||||
LOAD_16kb
|
|
||||||
;-------------------------------------------------------------------------------------
|
|
||||||
;------------------------- II ----------------------------------------
|
|
||||||
;----------- Open 2snd Page = ROM
|
|
||||||
LD A,(block_16kB_cnt) ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> A
|
|
||||||
INC A ; block_16kB_cnt+1 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> 1
|
|
||||||
LD (block_16kB_cnt), A ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
||||||
;CALL COM_TX
|
|
||||||
;-----------
|
|
||||||
LD C, A ;page
|
|
||||||
LD DE,#0000 ;offset in Win3:
|
|
||||||
LD B,32 ;1 block-512Byte // 32- 16kB
|
|
||||||
;-load data from opened file-------
|
|
||||||
LD A, #3 ;LOAD512(TSFAT.ASM)
|
|
||||||
CALL FAT_DRV ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 16kB
|
|
||||||
JR NZ,EXIT_FAT32_LOADER ;EOF -EXIT
|
|
||||||
;-----------CHECK CNT--------------------------------------------
|
|
||||||
LD A,(block_16kB_cnt) ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20> A
|
|
||||||
SUB TOTAL_PAGE ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><><EFBFBD> <20><><EFBFBD>
|
|
||||||
JR NZ,LOAD_16kb ; <20><><EFBFBD><EFBFBD> <20><> <20><> <20><><EFBFBD><EFBFBD><EFBFBD>, <20><><EFBFBD><EFBFBD> <20><><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>
|
|
||||||
; LOAD_16kb
|
|
||||||
;=================================================================
|
|
||||||
;---------------
|
|
||||||
; JP VS_INIT
|
|
||||||
; JP RESET_LOADER
|
|
||||||
EXIT_FAT32_LOADER
|
|
||||||
RET;
|
|
||||||
;------------------------------------------------------------------------------
|
|
||||||
ERR
|
|
||||||
;------------------------------------------------------------------------------
|
|
||||||
LD A,#02 ; ERROR: BORDER -RED!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
|
||||||
OUT (#FE),A ;
|
|
||||||
HALT
|
|
||||||
;==============================================================================
|
|
||||||
;------------------------------------------------------------------------------
|
|
||||||
; VS1053 Init
|
|
||||||
;------------------------------------------------------------------------------
|
|
||||||
VS_INIT
|
|
||||||
LD A,%00000000 ; XCS=0 XDCS=0
|
|
||||||
OUT (#05),A
|
|
||||||
LD HL,TABLE
|
|
||||||
LD B,44
|
|
||||||
VS_INIT1 LD D,(HL)
|
|
||||||
CALL VS_RW ; WR D ==>
|
|
||||||
INC HL
|
|
||||||
DJNZ VS_INIT1
|
|
||||||
LD A,%00100000 ; XCS=0 XDCS=1
|
|
||||||
OUT (#05),A
|
|
||||||
RET
|
|
||||||
;==============================================================================
|
|
||||||
|
|
||||||
;----------------RESTART-------------------------------------------------------
|
|
||||||
RESET_LOADER
|
|
||||||
;---ESTORE PAGE3
|
|
||||||
LD BC,PW3,A,(PGR3):OUT (C),A
|
|
||||||
;---ESTORE PAGE2
|
|
||||||
LD BC,PW2,A,(PGR) :OUT (C),A
|
|
||||||
;--------------------------------------------------
|
|
||||||
LD A,%00000100 ; Bit2 = 0:Loader ON, 1:Loader OFF;
|
|
||||||
LD BC,#0001
|
|
||||||
OUT (C),A ; RESET LOADER
|
|
||||||
LD SP,#FFFF
|
|
||||||
JP #0000 ; RESTART SYSTEM
|
|
||||||
;// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD><EFBFBD> 0x0000, LOADER OFF !!!!!!!!!
|
|
||||||
;================================ DRIVER ======================================
|
|
||||||
;========TS-Labs==================================
|
|
||||||
INCLUDE "tsfat/TSFAT.ASM" ;
|
|
||||||
;---------------BANK2----------------------
|
|
||||||
PGR3 EQU STRMED+1 ;
|
|
||||||
block_16kB_cnt EQU STRMED+2 ;
|
|
||||||
|
|
||||||
;------------------------------------------------------------------------------
|
|
||||||
; VS1053
|
|
||||||
;------------------------------------------------------------------------------
|
|
||||||
VS_RW
|
|
||||||
IN A,(#05)
|
|
||||||
RLCA
|
|
||||||
JR C,VS_RW
|
|
||||||
RLCA
|
|
||||||
JR NC,VS_RW
|
|
||||||
LD A,D
|
|
||||||
OUT (#04), A ; WR DATA
|
|
||||||
|
|
||||||
VS_RW1 IN A,(#05)
|
|
||||||
RLCA
|
|
||||||
JR C,VS_RW1
|
|
||||||
RLCA
|
|
||||||
JR NC,VS_RW1
|
|
||||||
IN A,(#04)
|
|
||||||
RET
|
|
||||||
|
|
||||||
TABLE DB #52,#49,#46,#46,#FF,#FF,#FF,#FF ;REFF....
|
|
||||||
DB #57,#41,#56,#45,#66,#6D,#74,#20 ;WAVEfmt
|
|
||||||
DB #10
|
|
||||||
DB #00,#00,#00,#01,#00,#02,#00
|
|
||||||
|
|
||||||
DB #80,#BB,#00,#00 ;48kHz
|
|
||||||
DB #00,#EE,#02,#00
|
|
||||||
|
|
||||||
DB #04,#00
|
|
||||||
DB #10,#00
|
|
||||||
DB #64,#61,#74,#61 ;data
|
|
||||||
DB #FF,#FF,#FF,#FF
|
|
||||||
;===================== COM_TX ================================
|
|
||||||
;COM_TX
|
|
||||||
; PUSH BC
|
|
||||||
; LD BC, #F8EF
|
|
||||||
; OUT (C), A
|
|
||||||
; POP BC
|
|
||||||
; RET
|
|
||||||
;=============================================================
|
|
||||||
savebin "loader.bin",Start, 8192
|
|
||||||
;savebin "loader.bin",Start, 2048 ;-2K
|
|
||||||
|
|
||||||
|
|
||||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@ -1,7 +0,0 @@
|
|||||||
#!/bin/sh
|
|
||||||
|
|
||||||
rm loader.bin
|
|
||||||
rm loader.hex
|
|
||||||
./sjasmplus loader.asm
|
|
||||||
./bin2hex.py --binaries=0,loader.bin
|
|
||||||
|
|
||||||
@ -1 +0,0 @@
|
|||||||
;--------------------------------------------------------------------------------
|
|
||||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -1 +0,0 @@
|
|||||||
;---------------------------------------
|
|
||||||
File diff suppressed because one or more lines are too long
256
src/tsconf.v
256
src/tsconf.v
@ -87,7 +87,6 @@ module tsconf(
|
|||||||
output SD_CS_N,
|
output SD_CS_N,
|
||||||
|
|
||||||
// General Sound
|
// General Sound
|
||||||
input GS_ENA,
|
|
||||||
output [21:0] GS_ADDR,
|
output [21:0] GS_ADDR,
|
||||||
output [7:0] GS_DI,
|
output [7:0] GS_DI,
|
||||||
input [7:0] GS_DO,
|
input [7:0] GS_DO,
|
||||||
@ -126,6 +125,7 @@ wire cpu_m1_n;
|
|||||||
wire cpu_rfsh_n;
|
wire cpu_rfsh_n;
|
||||||
wire [1:0] turbo;
|
wire [1:0] turbo;
|
||||||
wire [7:0] im2vect;
|
wire [7:0] im2vect;
|
||||||
|
|
||||||
// zsignal
|
// zsignal
|
||||||
wire cpu_stall; // zmem -> zclock
|
wire cpu_stall; // zmem -> zclock
|
||||||
wire cpu_req; // zmem -> arbiter
|
wire cpu_req; // zmem -> arbiter
|
||||||
@ -136,12 +136,9 @@ wire cpu_strobe; // arbiter -> zmem
|
|||||||
wire cpu_latch; // arbiter -> zmem
|
wire cpu_latch; // arbiter -> zmem
|
||||||
wire [23:0] cpu_addr;
|
wire [23:0] cpu_addr;
|
||||||
wire [20:0] cpu_addr_20;
|
wire [20:0] cpu_addr_20;
|
||||||
wire [2:0] cpu_addr_ext;
|
|
||||||
wire csvrom;
|
wire csvrom;
|
||||||
wire curr_cpu;
|
wire curr_cpu;
|
||||||
// Memory
|
|
||||||
wire [7:0] rom_do_bus;
|
|
||||||
wire [3:0] cacheconf;
|
|
||||||
// SDRAM
|
// SDRAM
|
||||||
wire [7:0] sdr_do_bus;
|
wire [7:0] sdr_do_bus;
|
||||||
wire [15:0] sdr_do_bus_16;
|
wire [15:0] sdr_do_bus_16;
|
||||||
@ -155,34 +152,10 @@ wire [1:0] dram_bsel;
|
|||||||
wire [15:0] dram_wrdata;
|
wire [15:0] dram_wrdata;
|
||||||
wire dram_req;
|
wire dram_req;
|
||||||
wire dram_rnw;
|
wire dram_rnw;
|
||||||
// Port
|
|
||||||
reg [7:0] port_xxfe_reg;
|
|
||||||
reg [7:0] port_xx01_reg;
|
|
||||||
reg [5:0] ena_cnt;
|
|
||||||
// System
|
|
||||||
wire reset;
|
|
||||||
//signal key_reset : std_logic;
|
|
||||||
reg loader;
|
|
||||||
wire zports_loader;
|
|
||||||
wire dos;
|
wire dos;
|
||||||
//signal xtpage_0 : std_logic_vector(7 downto 0);
|
|
||||||
// PS/2 Keyboard
|
|
||||||
wire [4:0] kb_do_bus;
|
|
||||||
wire [4:0] kb_f_bus;
|
|
||||||
wire [7:0] key_scancode;
|
|
||||||
// MC146818A
|
|
||||||
wire mc146818a_wr;
|
|
||||||
//signal mc146818a_rd : std_logic;
|
|
||||||
wire [7:0] mc146818a_do_bus;
|
|
||||||
wire port_bff7;
|
|
||||||
reg [7:0] port_eff7_reg;
|
|
||||||
reg ena_0_4375mhz;
|
|
||||||
wire [7:0] gluclock_addr;
|
wire [7:0] gluclock_addr;
|
||||||
// Soundrive
|
|
||||||
wire [7:0] covox_a;
|
|
||||||
wire [7:0] covox_b;
|
|
||||||
wire [7:0] covox_c;
|
|
||||||
wire [7:0] covox_d;
|
|
||||||
// clock
|
// clock
|
||||||
wire f0;
|
wire f0;
|
||||||
wire f1;
|
wire f1;
|
||||||
@ -192,21 +165,15 @@ wire c0;
|
|||||||
wire c1;
|
wire c1;
|
||||||
wire c2;
|
wire c2;
|
||||||
wire c3;
|
wire c3;
|
||||||
wire ay_clk;
|
|
||||||
wire zclk;
|
wire zclk;
|
||||||
wire zpos;
|
wire zpos;
|
||||||
wire zneg;
|
wire zneg;
|
||||||
//signal dos_on : std_logic;
|
|
||||||
//signal dos_off : std_logic;
|
|
||||||
wire vdos;
|
wire vdos;
|
||||||
wire pre_vdos;
|
wire pre_vdos;
|
||||||
wire vdos_off;
|
wire vdos_off;
|
||||||
wire vdos_on;
|
wire vdos_on;
|
||||||
wire dos_change;
|
wire dos_change;
|
||||||
//signal dos_stall : std_logic;
|
|
||||||
// out zsignals
|
|
||||||
wire m1;
|
wire m1;
|
||||||
//signal rfsh : std_logic;
|
|
||||||
wire rd;
|
wire rd;
|
||||||
wire wr;
|
wire wr;
|
||||||
wire iorq;
|
wire iorq;
|
||||||
@ -217,19 +184,15 @@ wire iowr;
|
|||||||
wire iorw;
|
wire iorw;
|
||||||
wire memrd;
|
wire memrd;
|
||||||
wire memwr;
|
wire memwr;
|
||||||
//signal memrw : std_logic;
|
|
||||||
wire opfetch;
|
wire opfetch;
|
||||||
wire intack;
|
wire intack;
|
||||||
// strobre
|
|
||||||
wire iorq_s;
|
wire iorq_s;
|
||||||
//signal mreq_s : std_logic;
|
|
||||||
wire iord_s;
|
wire iord_s;
|
||||||
wire iowr_s;
|
wire iowr_s;
|
||||||
wire iorw_s;
|
wire iorw_s;
|
||||||
//signal memrd_s : std_logic;
|
|
||||||
wire memwr_s;
|
wire memwr_s;
|
||||||
//signal memrw_s : std_logic;
|
|
||||||
wire opfetch_s;
|
wire opfetch_s;
|
||||||
|
|
||||||
// zports OUT
|
// zports OUT
|
||||||
wire [7:0] dout_ports;
|
wire [7:0] dout_ports;
|
||||||
wire ena_ports;
|
wire ena_ports;
|
||||||
@ -237,15 +200,11 @@ wire [31:0] xt_page;
|
|||||||
wire [4:0] fmaddr;
|
wire [4:0] fmaddr;
|
||||||
wire [7:0] sysconf;
|
wire [7:0] sysconf;
|
||||||
wire [7:0] memconf;
|
wire [7:0] memconf;
|
||||||
//signal fddvirt : std_logic_vector(3 downto 0);
|
|
||||||
//signal im2v_frm : std_logic_vector(2 downto 0);
|
|
||||||
//signal im2v_lin : std_logic_vector(2 downto 0);
|
|
||||||
//signal im2v_dma : std_logic_vector(2 downto 0);
|
|
||||||
wire [7:0] intmask;
|
wire [7:0] intmask;
|
||||||
wire [8:0] dmaport_wr;
|
wire [8:0] dmaport_wr;
|
||||||
//signal mus_in_TS : std_logic_vector(7 downto 0);
|
|
||||||
// VIDEO_TS
|
|
||||||
wire go_arbiter;
|
wire go_arbiter;
|
||||||
|
wire [3:0] cacheconf;
|
||||||
|
|
||||||
// z80
|
// z80
|
||||||
wire [15:0] zmd;
|
wire [15:0] zmd;
|
||||||
wire [7:0] zma;
|
wire [7:0] zma;
|
||||||
@ -277,32 +236,36 @@ wire sgpage_wr;
|
|||||||
wire hint_beg_wr;
|
wire hint_beg_wr;
|
||||||
wire vint_begl_wr;
|
wire vint_begl_wr;
|
||||||
wire vint_begh_wr;
|
wire vint_begh_wr;
|
||||||
|
|
||||||
// ZX controls
|
// ZX controls
|
||||||
wire res;
|
wire res;
|
||||||
wire int_start_frm;
|
wire int_start_frm;
|
||||||
wire int_start_lin;
|
wire int_start_lin;
|
||||||
|
|
||||||
// DRAM interface
|
// DRAM interface
|
||||||
wire [20:0] video_addr;
|
wire [20:0] video_addr;
|
||||||
wire [4:0] video_bw;
|
wire [4:0] video_bw;
|
||||||
wire video_go;
|
wire video_go;
|
||||||
wire [15:0] dram_rdata; // raw, should be latched by c2 (video_next)
|
|
||||||
wire video_next;
|
wire video_next;
|
||||||
wire video_pre_next;
|
wire video_pre_next;
|
||||||
wire next_video;
|
wire next_video;
|
||||||
wire video_strobe;
|
wire video_strobe;
|
||||||
wire video_next_strobe;
|
wire video_next_strobe;
|
||||||
|
|
||||||
// TS
|
// TS
|
||||||
wire [20:0] ts_addr;
|
wire [20:0] ts_addr;
|
||||||
wire ts_req;
|
wire ts_req;
|
||||||
wire ts_z80_lp;
|
wire ts_z80_lp;
|
||||||
|
|
||||||
// IN
|
// IN
|
||||||
wire ts_pre_next;
|
wire ts_pre_next;
|
||||||
wire ts_next;
|
wire ts_next;
|
||||||
|
|
||||||
// TM
|
// TM
|
||||||
wire [20:0] tm_addr;
|
wire [20:0] tm_addr;
|
||||||
wire tm_req;
|
wire tm_req;
|
||||||
// Video
|
|
||||||
wire tm_next;
|
wire tm_next;
|
||||||
|
|
||||||
// DMA
|
// DMA
|
||||||
wire dma_rnw;
|
wire dma_rnw;
|
||||||
wire dma_req;
|
wire dma_req;
|
||||||
@ -313,6 +276,7 @@ wire dma_next;
|
|||||||
wire dma_act;
|
wire dma_act;
|
||||||
wire dma_cram_we;
|
wire dma_cram_we;
|
||||||
wire dma_sfile_we;
|
wire dma_sfile_we;
|
||||||
|
|
||||||
// zmap
|
// zmap
|
||||||
wire [15:0] dma_data;
|
wire [15:0] dma_data;
|
||||||
wire [7:0] dma_wraddr;
|
wire [7:0] dma_wraddr;
|
||||||
@ -325,25 +289,9 @@ wire [7:0] dma_spi_din;
|
|||||||
wire cpu_spi_req;
|
wire cpu_spi_req;
|
||||||
wire [7:0] cpu_spi_din;
|
wire [7:0] cpu_spi_din;
|
||||||
wire [7:0] spi_dout;
|
wire [7:0] spi_dout;
|
||||||
// HDMI
|
|
||||||
wire clk_hdmi;
|
|
||||||
wire csync_ts;
|
|
||||||
wire hdmi_d1_sig;
|
|
||||||
|
|
||||||
wire [7:0] mouse_do;
|
wire [7:0] mouse_do;
|
||||||
|
|
||||||
// General Sound
|
|
||||||
wire [14:0] gs_l;
|
|
||||||
wire [14:0] gs_r;
|
|
||||||
wire [7:0] gs_do_bus;
|
|
||||||
wire gs_sel;
|
|
||||||
reg ce_gs;
|
|
||||||
|
|
||||||
// SAA1099
|
|
||||||
wire saa_wr_n;
|
|
||||||
wire [7:0] saa_out_l;
|
|
||||||
wire [7:0] saa_out_r;
|
|
||||||
wire ce_saa;
|
|
||||||
|
|
||||||
clock TS01
|
clock TS01
|
||||||
(
|
(
|
||||||
@ -437,7 +385,7 @@ zports TS05
|
|||||||
.dataout(ena_ports),
|
.dataout(ena_ports),
|
||||||
.a(cpu_a_bus),
|
.a(cpu_a_bus),
|
||||||
.rst(reset),
|
.rst(reset),
|
||||||
.loader(zports_loader), //loader, -- for load ROM, SPI should be enable
|
.loader(0), //loader, -- for load ROM, SPI should be enable
|
||||||
.opfetch(opfetch), // from zsignals
|
.opfetch(opfetch), // from zsignals
|
||||||
.rd(rd),
|
.rd(rd),
|
||||||
.wr(wr),
|
.wr(wr),
|
||||||
@ -482,9 +430,6 @@ zports TS05
|
|||||||
.sysconf(sysconf),
|
.sysconf(sysconf),
|
||||||
.memconf(memconf),
|
.memconf(memconf),
|
||||||
.cacheconf(cacheconf),
|
.cacheconf(cacheconf),
|
||||||
//im2v_frm => im2v_frm,
|
|
||||||
//im2v_lin => im2v_lin,
|
|
||||||
//im2v_dma => im2v_dma,
|
|
||||||
.intmask(intmask),
|
.intmask(intmask),
|
||||||
.dmaport_wr(dmaport_wr), // dmaport_wr
|
.dmaport_wr(dmaport_wr), // dmaport_wr
|
||||||
.dma_act(dma_act), // from DMA (status of DMA)
|
.dma_act(dma_act), // from DMA (status of DMA)
|
||||||
@ -494,14 +439,6 @@ zports TS05
|
|||||||
.vdos_off(vdos_off),
|
.vdos_off(vdos_off),
|
||||||
.rstrom(2'b11),
|
.rstrom(2'b11),
|
||||||
.tape_read(1'b1),
|
.tape_read(1'b1),
|
||||||
// ide_in => "0000000000000000",
|
|
||||||
// ide_out => open,
|
|
||||||
// ide_cs0_n => open,
|
|
||||||
// ide_cs1_n => open,
|
|
||||||
// ide_req => open,
|
|
||||||
// ide_stb => '0',
|
|
||||||
// ide_ready => '0',
|
|
||||||
// ide_stall => open,
|
|
||||||
.keys_in(kb_do_bus), // keys (port FE)
|
.keys_in(kb_do_bus), // keys (port FE)
|
||||||
.mus_in(mouse_do), // mouse (xxDF)
|
.mus_in(mouse_do), // mouse (xxDF)
|
||||||
.kj_in(joystick),
|
.kj_in(joystick),
|
||||||
@ -552,13 +489,12 @@ zmem TS06
|
|||||||
.cpu_req(cpu_req),
|
.cpu_req(cpu_req),
|
||||||
.cpu_addr(cpu_addr_20),
|
.cpu_addr(cpu_addr_20),
|
||||||
.cpu_wrbsel(cpu_wrbsel), // for 16bit data
|
.cpu_wrbsel(cpu_wrbsel), // for 16bit data
|
||||||
//cpu_rddata=> sdr_do_bus_16, -- RD from SDRAM (cpu_strobe=HI and clk)
|
|
||||||
.cpu_rddata(sdr2cpu_do_bus_16),
|
.cpu_rddata(sdr2cpu_do_bus_16),
|
||||||
.cpu_next(cpu_next),
|
.cpu_next(cpu_next),
|
||||||
.cpu_strobe(cpu_strobe), // from ARBITER ACTIVE=HI
|
.cpu_strobe(cpu_strobe), // from ARBITER ACTIVE=HI
|
||||||
.cpu_latch(cpu_latch),
|
.cpu_latch(cpu_latch),
|
||||||
.cpu_stall(cpu_stall), // for Zclock if HI-> STALL (ZCLK)
|
.cpu_stall(cpu_stall), // for Zclock if HI-> STALL (ZCLK)
|
||||||
.loader(loader), // ROM for loader active
|
.loader(0), // ROM for loader active
|
||||||
.testkey(1'b1),
|
.testkey(1'b1),
|
||||||
.intt(1'b0)
|
.intt(1'b0)
|
||||||
);
|
);
|
||||||
@ -583,8 +519,7 @@ arbiter TS07
|
|||||||
.video_strobe(video_strobe), // (c3) one-cycle strobe meaning that video_data is available
|
.video_strobe(video_strobe), // (c3) one-cycle strobe meaning that video_data is available
|
||||||
.video_next_strobe(video_next_strobe),
|
.video_next_strobe(video_next_strobe),
|
||||||
.next_vid(next_video), // used for TM prefetch
|
.next_vid(next_video), // used for TM prefetch
|
||||||
//cpu_addr => cpu_addr,
|
.cpu_addr({csvrom, 2'b00, cpu_addr_20}),
|
||||||
.cpu_addr({cpu_addr_ext, cpu_addr_20}),
|
|
||||||
.cpu_wrdata(cpu_do_bus),
|
.cpu_wrdata(cpu_do_bus),
|
||||||
.cpu_req(cpu_req),
|
.cpu_req(cpu_req),
|
||||||
.cpu_rnw(rd),
|
.cpu_rnw(rd),
|
||||||
@ -666,7 +601,7 @@ video_top TS08
|
|||||||
.video_addr(video_addr),
|
.video_addr(video_addr),
|
||||||
.video_bw(video_bw),
|
.video_bw(video_bw),
|
||||||
.video_go(go_arbiter),
|
.video_go(go_arbiter),
|
||||||
.dram_rdata(dram_rdata), // raw, should be latched by c2 (video_next)
|
.dram_rdata(sdr_do_bus_16), // raw, should be latched by c2 (video_next)
|
||||||
.video_next(video_next),
|
.video_next(video_next),
|
||||||
.video_pre_next(video_pre_next),
|
.video_pre_next(video_pre_next),
|
||||||
.next_video(next_video),
|
.next_video(next_video),
|
||||||
@ -758,20 +693,18 @@ zint TS13
|
|||||||
.int_start_dma(int_start_dma), //< N3 DMA
|
.int_start_dma(int_start_dma), //< N3 DMA
|
||||||
.vdos(pre_vdos), // vdos,--pre_vdos
|
.vdos(pre_vdos), // vdos,--pre_vdos
|
||||||
.intack(intack), //< zsignals === (intack ? im2vect : 8'hFF)));
|
.intack(intack), //< zsignals === (intack ? im2vect : 8'hFF)));
|
||||||
//im2v_frm => im2v_frm, --< ZPORT (2 downto 0);
|
|
||||||
//im2v_lin => im2v_lin, --< ZPORT (2 downto 0);
|
|
||||||
//im2v_dma => im2v_dma, --< ZPORT (2 downto 0);
|
|
||||||
.intmask(intmask), //< ZPORT (7 downto 0);
|
.intmask(intmask), //< ZPORT (7 downto 0);
|
||||||
.im2vect(im2vect), //> CPU Din (2 downto 0);
|
.im2vect(im2vect), //> CPU Din (2 downto 0);
|
||||||
.int_n(cpu_int_n_TS)
|
.int_n(cpu_int_n_TS)
|
||||||
);
|
);
|
||||||
|
|
||||||
// ROM
|
// BIOS
|
||||||
dpram #(.ADDRWIDTH(13), .MEM_INIT_FILE("src/loader_fat32/loader.mif")) SE1
|
wire [7:0] bios_do_bus;
|
||||||
|
dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE("tsbios.mif")) BIOS
|
||||||
(
|
(
|
||||||
.clock(clk_28mhz),
|
.clock(clk_28mhz),
|
||||||
.address_a(cpu_a_bus[12:0]),
|
.address_a({cpu_addr_20[14:0],cpu_wrbsel}),
|
||||||
.q_a(rom_do_bus)
|
.q_a(bios_do_bus)
|
||||||
);
|
);
|
||||||
|
|
||||||
// SDRAM Controller
|
// SDRAM Controller
|
||||||
@ -782,7 +715,7 @@ sdram SE4
|
|||||||
.c0(c0),
|
.c0(c0),
|
||||||
.c3(c3),
|
.c3(c3),
|
||||||
.curr_cpu(curr_cpu), // from arbiter for luch DO_cpu
|
.curr_cpu(curr_cpu), // from arbiter for luch DO_cpu
|
||||||
.loader(loader), // loader = 1: wr to ROM
|
.loader(0), // loader = 1: wr to ROM
|
||||||
.bsel(dram_bsel),
|
.bsel(dram_bsel),
|
||||||
.a(dram_addr),
|
.a(dram_addr),
|
||||||
.di(dram_wrdata),
|
.di(dram_wrdata),
|
||||||
@ -802,6 +735,12 @@ sdram SE4
|
|||||||
.dqmh(SDRAM_DQMH)
|
.dqmh(SDRAM_DQMH)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// PS/2 Keyboard
|
||||||
|
wire [4:0] kb_do_bus;
|
||||||
|
wire [4:0] kb_f_bus;
|
||||||
|
wire [7:0] key_scancode;
|
||||||
|
|
||||||
keyboard SE5
|
keyboard SE5
|
||||||
(
|
(
|
||||||
.clk(clk_28mhz),
|
.clk(clk_28mhz),
|
||||||
@ -822,6 +761,24 @@ kempston_mouse KM
|
|||||||
.dout(mouse_do)
|
.dout(mouse_do)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
// MC146818A,RTC
|
||||||
|
wire mc146818a_wr = port_bff7 && ~cpu_wr_n;
|
||||||
|
wire [7:0] mc146818a_do_bus;
|
||||||
|
wire port_bff7 = ~cpu_iorq_n && cpu_a_bus == 16'hBFF7 && cpu_m1_n && port_eff7_reg[7];
|
||||||
|
|
||||||
|
reg ena_0_4375mhz;
|
||||||
|
always @(negedge clk_28mhz) begin
|
||||||
|
reg [5:0] div;
|
||||||
|
div <= div + 1'd1;
|
||||||
|
ena_0_4375mhz <= !div; //28MHz/64
|
||||||
|
end
|
||||||
|
|
||||||
|
reg [7:0] port_eff7_reg;
|
||||||
|
always @(posedge clk_28mhz) begin
|
||||||
|
if (reset) port_eff7_reg <= 0;
|
||||||
|
else if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus == 16'hEFF7) port_eff7_reg <= cpu_do_bus; //for RTC
|
||||||
|
end
|
||||||
|
|
||||||
mc146818a SE9
|
mc146818a SE9
|
||||||
(
|
(
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
@ -837,7 +794,13 @@ mc146818a SE9
|
|||||||
.do(mc146818a_do_bus)
|
.do(mc146818a_do_bus)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
// Soundrive
|
// Soundrive
|
||||||
|
wire [7:0] covox_a;
|
||||||
|
wire [7:0] covox_b;
|
||||||
|
wire [7:0] covox_c;
|
||||||
|
wire [7:0] covox_d;
|
||||||
|
|
||||||
soundrive SE10
|
soundrive SE10
|
||||||
(
|
(
|
||||||
.reset(reset),
|
.reset(reset),
|
||||||
@ -854,6 +817,7 @@ soundrive SE10
|
|||||||
.outd(covox_d)
|
.outd(covox_d)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
// Turbosound FM
|
||||||
reg ce_ym, ce_cpu;
|
reg ce_ym, ce_cpu;
|
||||||
always @(posedge clk_28mhz) begin
|
always @(posedge clk_28mhz) begin
|
||||||
reg [1:0] div;
|
reg [1:0] div;
|
||||||
@ -865,8 +829,8 @@ always @(posedge clk_28mhz) begin
|
|||||||
if(ce_cpu) ce_cpu <= 0;
|
if(ce_cpu) ce_cpu <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
wire ts_enable = cpu_a_bus[0] & cpu_a_bus[15] & ~cpu_a_bus[1];
|
wire ts_enable = ~cpu_iorq_n & cpu_a_bus[0] & cpu_a_bus[15] & ~cpu_a_bus[1];
|
||||||
wire ts_we = ts_enable & ~cpu_iorq_n & ~cpu_wr_n;
|
wire ts_we = ts_enable & ~cpu_wr_n;
|
||||||
|
|
||||||
wire [11:0] ts_l, ts_r;
|
wire [11:0] ts_l, ts_r;
|
||||||
wire [7:0] ts_do;
|
wire [7:0] ts_do;
|
||||||
@ -886,11 +850,19 @@ turbosound SE12
|
|||||||
.CHANNEL_R(ts_r)
|
.CHANNEL_R(ts_r)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// General Sound
|
||||||
|
reg ce_gs;
|
||||||
always @(posedge clk_84mhz) begin
|
always @(posedge clk_84mhz) begin
|
||||||
ce_gs <= clk_28mhz;
|
ce_gs <= clk_28mhz;
|
||||||
if(ce_gs) ce_gs <= 0;
|
if(ce_gs) ce_gs <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
wire [14:0] gs_l;
|
||||||
|
wire [14:0] gs_r;
|
||||||
|
wire [7:0] gs_do_bus;
|
||||||
|
wire gs_sel = ~cpu_iorq_n & cpu_m1_n & (cpu_a_bus[7:4] == 'hB && cpu_a_bus[2:0] == 'h3);
|
||||||
|
|
||||||
gs #("src/sound/gs105b.mif") U15
|
gs #("src/sound/gs105b.mif") U15
|
||||||
(
|
(
|
||||||
.RESET(reset),
|
.RESET(reset),
|
||||||
@ -900,7 +872,7 @@ gs #("src/sound/gs105b.mif") U15
|
|||||||
.A(cpu_a_bus[3]),
|
.A(cpu_a_bus[3]),
|
||||||
.DI(cpu_do_bus),
|
.DI(cpu_do_bus),
|
||||||
.DO(gs_do_bus),
|
.DO(gs_do_bus),
|
||||||
.CS_n(cpu_iorq_n | (~gs_sel)),
|
.CS_n(cpu_iorq_n | ~gs_sel),
|
||||||
.WR_n(cpu_wr_n),
|
.WR_n(cpu_wr_n),
|
||||||
.RD_n(cpu_rd_n),
|
.RD_n(cpu_rd_n),
|
||||||
|
|
||||||
@ -915,6 +887,13 @@ gs #("src/sound/gs105b.mif") U15
|
|||||||
.OUTR(gs_r)
|
.OUTR(gs_r)
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
// SAA1099
|
||||||
|
wire [7:0] saa_out_l;
|
||||||
|
wire [7:0] saa_out_r;
|
||||||
|
wire ce_saa;
|
||||||
|
wire saa_wr_n = ~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFF && ~dos;
|
||||||
|
|
||||||
saa1099 U16
|
saa1099 U16
|
||||||
(
|
(
|
||||||
.clk_sys(clk_28mhz),
|
.clk_sys(clk_28mhz),
|
||||||
@ -928,68 +907,6 @@ saa1099 U16
|
|||||||
.out_r(saa_out_r)
|
.out_r(saa_out_r)
|
||||||
);
|
);
|
||||||
|
|
||||||
//-----------------------------------------------------------------------------
|
|
||||||
// Global
|
|
||||||
//-----------------------------------------------------------------------------
|
|
||||||
assign reset = COLD_RESET | WARM_RESET | kb_f_bus[1]; // Reset
|
|
||||||
assign RESET_OUT = reset;
|
|
||||||
|
|
||||||
always @(negedge clk_28mhz) begin
|
|
||||||
ena_cnt <= ena_cnt + 1'd1;
|
|
||||||
ena_0_4375mhz <= ~ena_cnt[5] & ena_cnt[4] & ena_cnt[3] & ena_cnt[2] & ena_cnt[1] & ena_cnt[0];
|
|
||||||
end
|
|
||||||
|
|
||||||
// CPU interface
|
|
||||||
assign cpu_addr_ext = (loader && (cpu_a_bus[15:14] == 2'b10 || cpu_a_bus[15:14] == 2'b11)) ? 3'b100 : {csvrom, 2'b00};
|
|
||||||
|
|
||||||
assign dram_rdata = sdr_do_bus_16;
|
|
||||||
|
|
||||||
assign gs_sel = (GS_ENA && ~cpu_iorq_n && cpu_m1_n && cpu_a_bus[7:4] == 4'b1011 && cpu_a_bus[2:0] == 3'b011);
|
|
||||||
|
|
||||||
assign cpu_di_bus = (loader && ~cpu_mreq_n && ~cpu_rd_n && !cpu_a_bus[15:13]) ? rom_do_bus : // loader ROM
|
|
||||||
(~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM
|
|
||||||
(intack) ? im2vect :
|
|
||||||
(~cpu_iorq_n && ~cpu_rd_n && port_bff7 && port_eff7_reg[7]) ? mc146818a_do_bus : // MC146818A
|
|
||||||
(gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound
|
|
||||||
(~cpu_iorq_n && ~cpu_rd_n && ts_enable) ? ts_do : // TurboSound
|
|
||||||
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus == 16'h0001) ? key_scancode :
|
|
||||||
(ena_ports) ? dout_ports :
|
|
||||||
8'b11111111;
|
|
||||||
|
|
||||||
assign zports_loader = loader & ~port_xx01_reg[0]; // enable zports_loader only for SPI flash loading mode
|
|
||||||
|
|
||||||
always @(posedge clk_28mhz) begin
|
|
||||||
if(COLD_RESET) begin
|
|
||||||
port_xx01_reg <= 1; // bit2 = (0:Loader ON, 1:Loader OFF); bit0 = (0:FLASH, 1:SD)
|
|
||||||
loader <= 1;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 1) port_xx01_reg <= cpu_do_bus;
|
|
||||||
if (~cpu_m1_n && ~cpu_mreq_n && !cpu_a_bus && port_xx01_reg[2]) loader <= 0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge clk_28mhz) begin
|
|
||||||
if (reset) begin
|
|
||||||
port_xxfe_reg <= 0;
|
|
||||||
port_eff7_reg <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFE) port_xxfe_reg <= cpu_do_bus;
|
|
||||||
if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus == 16'hEFF7) port_eff7_reg <= cpu_do_bus; //for RTC
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// TURBO
|
|
||||||
assign turbo = (loader) ? 2'b11 : sysconf[1:0];
|
|
||||||
|
|
||||||
// RTC
|
|
||||||
assign mc146818a_wr = port_bff7 && ~cpu_wr_n;
|
|
||||||
assign port_bff7 = ~cpu_iorq_n && cpu_a_bus == 16'hBFF7 && cpu_m1_n && port_eff7_reg[7];
|
|
||||||
|
|
||||||
// SAA1099
|
|
||||||
assign saa_wr_n = ~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFF && ~dos;
|
|
||||||
|
|
||||||
wire [11:0] audio_l = ts_l + {gs_l[14], gs_l[14:4]} + {2'b00, covox_a, 2'b00} + {2'b00, covox_b, 2'b00} + {1'b0, saa_out_l, 3'b000} + {3'b000, port_xxfe_reg[4], 8'b00000000};
|
wire [11:0] audio_l = ts_l + {gs_l[14], gs_l[14:4]} + {2'b00, covox_a, 2'b00} + {2'b00, covox_b, 2'b00} + {1'b0, saa_out_l, 3'b000} + {3'b000, port_xxfe_reg[4], 8'b00000000};
|
||||||
wire [11:0] audio_r = ts_r + {gs_r[14], gs_r[14:4]} + {2'b00, covox_c, 2'b00} + {2'b00, covox_d, 2'b00} + {1'b0, saa_out_r, 3'b000} + {3'b000, port_xxfe_reg[4], 8'b00000000};
|
wire [11:0] audio_r = ts_r + {gs_r[14], gs_r[14:4]} + {2'b00, covox_c, 2'b00} + {2'b00, covox_d, 2'b00} + {1'b0, saa_out_r, 3'b000} + {3'b000, port_xxfe_reg[4], 8'b00000000};
|
||||||
|
|
||||||
@ -1000,4 +917,31 @@ compressor compressor
|
|||||||
SOUND_L, SOUND_R
|
SOUND_L, SOUND_R
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
//-----------------------------------------------------------------------------
|
||||||
|
// Global
|
||||||
|
//-----------------------------------------------------------------------------
|
||||||
|
wire reset = COLD_RESET | WARM_RESET | kb_f_bus[1]; // Reset
|
||||||
|
assign RESET_OUT = reset;
|
||||||
|
|
||||||
|
// CPU interface
|
||||||
|
assign cpu_di_bus =
|
||||||
|
(csvrom && ~cpu_mreq_n && ~cpu_rd_n) ? bios_do_bus : // BIOS
|
||||||
|
(~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM
|
||||||
|
(intack) ? im2vect :
|
||||||
|
(port_bff7 && port_eff7_reg[7] && ~cpu_iorq_n && ~cpu_rd_n) ? mc146818a_do_bus : // MC146818A
|
||||||
|
(gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound
|
||||||
|
(ts_enable && ~cpu_rd_n) ? ts_do : // TurboSound
|
||||||
|
(cpu_a_bus == 16'h0001 && ~cpu_iorq_n && ~cpu_rd_n) ? key_scancode :
|
||||||
|
(ena_ports) ? dout_ports :
|
||||||
|
8'b11111111;
|
||||||
|
// TURBO
|
||||||
|
assign turbo = sysconf[1:0];
|
||||||
|
|
||||||
|
reg [7:0] port_xxfe_reg;
|
||||||
|
always @(posedge clk_28mhz) begin
|
||||||
|
if (reset) port_xxfe_reg <= 0;
|
||||||
|
else if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFE) port_xxfe_reg <= cpu_do_bus;
|
||||||
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
2753
tsbios.mif
Normal file
2753
tsbios.mif
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user