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Video cleanup.

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This commit is contained in:
sorgelig
2018-08-23 04:18:11 +08:00
parent 24267b7bc4
commit 5d9db127a9
4 changed files with 28 additions and 129 deletions
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20
src/video/video_mode.v
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@ -10,7 +10,6 @@ module video_mode
input wire [7:0] vpage, input wire [7:0] vpage,
input wire [7:0] vconf, input wire [7:0] vconf,
input wire ts_rres_ext, input wire ts_rres_ext,
input wire v60hz,
// video parameters & mode controls // video parameters & mode controls
input wire [8:0] gx_offs, input wire [8:0] gx_offs,
@ -31,7 +30,6 @@ module video_mode
input wire pix_start, input wire pix_start,
input wire line_start_s, input wire line_start_s,
output wire tv_hires, output wire tv_hires,
output reg vga_hires,
output wire [1:0] render_mode, output wire [1:0] render_mode,
output wire pix_stb, output wire pix_stb,
output wire fetch_stb, output wire fetch_stb,
@ -55,8 +53,6 @@ wire [1:0] rres = vconf[7:6];
// clocking strobe for pixels (TV) // clocking strobe for pixels (TV)
assign pix_stb = tv_hires ? f1 : c3; assign pix_stb = tv_hires ? f1 : c3;
always @(posedge clk) if (line_start_s) vga_hires <= tv_hires;
// Modes // Modes
localparam M_ZX = 2'h0; // ZX localparam M_ZX = 2'h0; // ZX
localparam M_HC = 2'h1; // 16c localparam M_HC = 2'h1; // 16c
@ -181,15 +177,15 @@ assign hp_end[1] = 9'd428; // 320
assign hp_end[2] = 9'd428; // 320 assign hp_end[2] = 9'd428; // 320
assign hp_end[3] = 9'd448; // 360 assign hp_end[3] = 9'd448; // 360
assign vp_beg[0] = v60hz ? 9'd046 : 9'd080; // 192 (22-24-192-24)/(32-48-192-48) (blank-border-pixels-border) assign vp_beg[0] = 9'd080; // 192 (22-24-192-24)/(32-48-192-48) (blank-border-pixels-border)
assign vp_beg[1] = v60hz ? 9'd042 : 9'd076; // 200 (22-20-200-20)/(32-44-200-44) assign vp_beg[1] = 9'd076; // 200 (22-20-200-20)/(32-44-200-44)
assign vp_beg[2] = v60hz ? 9'd022 : 9'd056; // 240 (22-0-240-0)/(32-24-240-24) assign vp_beg[2] = 9'd056; // 240 (22-0-240-0)/(32-24-240-24)
assign vp_beg[3] = v60hz ? 9'd022 : 9'd032; // 288 (22-0-240-0)/(32-0-288-0) assign vp_beg[3] = 9'd032; // 288 (22-0-240-0)/(32-0-288-0)
assign vp_end[0] = v60hz ? 9'd238 : 9'd272; // 192 assign vp_end[0] = 9'd272; // 192
assign vp_end[1] = v60hz ? 9'd242 : 9'd276; // 200 assign vp_end[1] = 9'd276; // 200
assign vp_end[2] = v60hz ? 9'd262 : 9'd296; // 240 assign vp_end[2] = 9'd296; // 240
assign vp_end[3] = v60hz ? 9'd262 : 9'd320; // 240/288 assign vp_end[3] = 9'd320; // 240/288
assign x_tile[0] = 6'd34; // 256 assign x_tile[0] = 6'd34; // 256
assign x_tile[1] = 6'd42; // 320 assign x_tile[1] = 6'd42; // 320

14
src/video/video_out.v
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@ -5,17 +5,14 @@
module video_out module video_out
( (
// clocks // clocks
input wire clk, f0, c3, input wire clk, c3,
// video controls // video controls
input wire vga_on,
input wire tv_blank, input wire tv_blank,
input wire vga_blank,
input wire [1:0] plex_sel_in, input wire [1:0] plex_sel_in,
// mode controls // mode controls
input wire tv_hires, input wire tv_hires,
input wire vga_hires,
input wire [3:0] palsel, input wire [3:0] palsel,
// Z80 pins // Z80 pins
@ -25,7 +22,6 @@ module video_out
// video data // video data
input wire [7:0] vplex_in, input wire [7:0] vplex_in,
input wire [7:0] vgaplex,
output wire [7:0] vred, output wire [7:0] vred,
output wire [7:0] vgrn, output wire [7:0] vgrn,
output wire [7:0] vblu, output wire [7:0] vblu,
@ -33,14 +29,10 @@ module video_out
); );
// TV/VGA mux
reg [7:0] vplex; reg [7:0] vplex;
always @(posedge clk) if (c3) vplex <= vplex_in; always @(posedge clk) if (c3) vplex <= vplex_in;
wire [7:0] plex = vga_on ? vgaplex : vplex; wire [7:0] vdata = tv_hires ? {palsel, plex_sel_in[1] ? vplex[3:0] : vplex[7:4]} : vplex;
wire plex_sel = vga_on ? plex_sel_in[0] : plex_sel_in[1];
wire hires = vga_on ? vga_hires : tv_hires;
wire [7:0] vdata = hires ? {palsel, plex_sel ? plex[3:0] : plex[7:4]} : plex;
// CRAM // CRAM
@ -56,7 +48,7 @@ dpram #(.DATAWIDTH(16), .ADDRWIDTH(8), .MEM_INIT_FILE("src/video/video_cram.mif"
); );
reg blank; reg blank;
always @(posedge clk) blank <= vga_on ? vga_blank : tv_blank; always @(posedge clk) blank <= tv_blank;
wire [14:0] vpix = blank ? 15'b0 : vpixel[14:0]; wire [14:0] vpix = blank ? 15'b0 : vpixel[14:0];

72
src/video/video_sync.v
View File

@ -26,13 +26,8 @@ module video_sync
// video syncs // video syncs
output reg hsync, output reg hsync,
output reg vsync, output reg vsync,
output reg csync,
// video controls // video controls
input wire cfg_60hz,
input wire sync_pol,
input wire vga_on,
output reg v60hz,
input wire nogfx, input wire nogfx,
output wire v_pf, output wire v_pf,
output wire hpix, output wire hpix,
@ -42,9 +37,6 @@ module video_sync
output wire hvtspix, output wire hvtspix,
output wire tv_hblank, output wire tv_hblank,
output wire tv_vblank, output wire tv_vblank,
output reg vga_hblank,
output reg vga_vblank,
output wire vga_line,
output wire frame_start, output wire frame_start,
output wire line_start_s, output wire line_start_s,
output wire pix_start, output wire pix_start,
@ -53,13 +45,11 @@ module video_sync
output wire flash, output wire flash,
// video counters // video counters
output wire [9:0] vga_cnt_in,
output wire [9:0] vga_cnt_out,
output wire [8:0] ts_raddr, output wire [8:0] ts_raddr,
output reg [8:0] lcount, output reg [8:0] lcount,
output reg [7:0] cnt_col, output reg [7:0] cnt_col,
output reg [8:0] cnt_row, output reg [8:0] cnt_row,
output reg cptr, output reg cptr,
output reg [3:0] scnt, output reg [3:0] scnt,
// DRAM // DRAM
@ -80,37 +70,21 @@ localparam HSYNCV_END = 9'd31;
localparam HBLNKV_END = 9'd42; localparam HBLNKV_END = 9'd42;
localparam HPERIOD = 9'd448; localparam HPERIOD = 9'd448;
localparam VSYNC_BEG_50 = 9'd08; localparam VSYNC_BEG = 9'd08;
localparam VSYNC_END_50 = 9'd11; localparam VSYNC_END = 9'd11;
localparam VBLNK_BEG_50 = 9'd00; localparam VBLNK_BEG = 9'd00;
localparam VBLNK_END_50 = 9'd32; localparam VBLNK_END = 9'd32;
localparam VPERIOD_50 = 9'd320; localparam VPERIOD = 9'd320;
localparam VSYNC_BEG_60 = 9'd04;
localparam VSYNC_END_60 = 9'd07;
localparam VBLNK_BEG_60 = 9'd00;
localparam VBLNK_END_60 = 9'd22;
localparam VPERIOD_60 = 9'd262;
wire [8:0] vsync_beg = v60hz ? VSYNC_BEG_60 : VSYNC_BEG_50;
wire [8:0] vsync_end = v60hz ? VSYNC_END_60 : VSYNC_END_50;
wire [8:0] vblnk_beg = v60hz ? VBLNK_BEG_60 : VBLNK_BEG_50;
wire [8:0] vblnk_end = v60hz ? VBLNK_END_60 : VBLNK_END_50;
wire [8:0] vperiod = v60hz ? VPERIOD_60 : VPERIOD_50;
// counters // counters
reg [8:0] hcount = 0; reg [8:0] hcount = 0;
reg [8:0] vcount = 0; reg [8:0] vcount = 0;
reg [8:0] cnt_out = 0;
// horizontal TV (7 MHz) // horizontal TV (7 MHz)
always @(posedge clk) if (c3) hcount <= line_start ? 9'b0 : hcount + 9'b1; always @(posedge clk) if (c3) hcount <= line_start ? 9'b0 : hcount + 9'b1;
// vertical TV (15.625 kHz) // vertical TV (15.625 kHz)
always @(posedge clk) if (line_start_s) vcount <= (vcount == (vperiod - 1)) ? 9'b0 : vcount + 9'b1; always @(posedge clk) if (line_start_s) vcount <= (vcount == (VPERIOD - 1)) ? 9'b0 : vcount + 9'b1;
// horizontal VGA (14MHz)
always @(posedge clk) if (f1) cnt_out <= vga_pix_start && c3 ? 9'b0 : cnt_out + 9'b1;
// column address for DRAM // column address for DRAM
always @(posedge clk) begin always @(posedge clk) begin
@ -133,11 +107,7 @@ end
// pixel counter // pixel counter
always @(posedge clk) if (pix_stb) scnt <= pix_start ? 4'b0 : scnt + 4'b1; // f1 or c3 always @(posedge clk) if (pix_stb) scnt <= pix_start ? 4'b0 : scnt + 4'b1; // f1 or c3
assign vga_cnt_in = {vcount[0], hcount - HBLNK_END}; // TS-line counter
assign vga_cnt_out = {~vcount[0], cnt_out};
// TS-line counter
assign ts_raddr = hcount - hpix_beg_ts; assign ts_raddr = hcount - hpix_beg_ts;
always @(posedge clk) if (ts_start_coarse) lcount <= vcount - vpix_beg_ts + 9'b1; always @(posedge clk) if (ts_start_coarse) lcount <= vcount - vpix_beg_ts + 9'b1;
@ -155,27 +125,16 @@ assign frame = flash_ctr[0];
assign flash = flash_ctr[4]; assign flash = flash_ctr[4];
always @(posedge clk) begin always @(posedge clk) begin
if (frame_start && c3) begin if (frame_start && c3) begin
v60hz <= !cfg_60hz; // re-sync of 60Hz mode selector
flash_ctr <= flash_ctr + 5'b1; flash_ctr <= flash_ctr + 5'b1;
end end
end end
// sync strobes // sync strobes
wire hs = (hcount >= HSYNC_BEG) && (hcount < HSYNC_END); wire hs = (hcount >= HSYNC_BEG) && (hcount < HSYNC_END);
wire vs = (vcount >= vsync_beg) && (vcount < vsync_end); wire vs = (vcount >= VSYNC_BEG) && (vcount < VSYNC_END);
assign tv_hblank = (hcount > HBLNK_BEG) && (hcount <= HBLNK_END); assign tv_hblank = (hcount > HBLNK_BEG) && (hcount <= HBLNK_END);
assign tv_vblank = (vcount >= vblnk_beg) && (vcount < vblnk_end); assign tv_vblank = (vcount >= VBLNK_BEG) && (vcount < VBLNK_END);
wire vga_hblank1 = (cnt_out > 9'd359);
always @(posedge clk) if (f1) vga_hblank <= vga_hblank1;
wire hs_vga = ((hcount >= HSYNCV_BEG) && (hcount < HSYNCV_END)) ||
((hcount >= (HSYNCV_BEG + HPERIOD/2)) && (hcount < (HSYNCV_END + HPERIOD/2)));
wire vga_pix_start = ((hcount == (HBLNKV_END)) || (hcount == (HBLNKV_END + HPERIOD/2)));
assign vga_line = (hcount >= HPERIOD/2);
assign hvpix = hpix && vpix; assign hvpix = hpix && vpix;
@ -195,19 +154,16 @@ always @(posedge clk) video_go <= (hcount >= (hpix_beg - go_offs - x_offs)) && (
wire line_start = hcount == (HPERIOD - 1); wire line_start = hcount == (HPERIOD - 1);
assign line_start_s = line_start && c3; assign line_start_s = line_start && c3;
wire line_start2 = hcount == (HSYNC_END - 1); wire line_start2 = hcount == (HSYNC_END - 1);
assign frame_start = line_start && (vcount == (vperiod - 1)); assign frame_start = line_start && (vcount == (VPERIOD - 1));
wire vis_start = line_start && (vcount == (vblnk_end - 1)); wire vis_start = line_start && (vcount == (VBLNK_END - 1));
assign pix_start = hcount == (hpix_beg - x_offs - 1); assign pix_start = hcount == (hpix_beg - x_offs - 1);
wire ts_start_coarse = hcount == (hpix_beg_ts - 1); wire ts_start_coarse = hcount == (hpix_beg_ts - 1);
assign ts_start = c3 && ts_start_coarse; assign ts_start = c3 && ts_start_coarse;
assign int_start = (hcount == {hint_beg, 1'b0}) && (vcount == vint_beg) && c0; assign int_start = (hcount == {hint_beg, 1'b0}) && (vcount == vint_beg) && c0;
always @(posedge clk) if (line_start_s) vga_vblank <= tv_vblank;
always @(posedge clk) begin always @(posedge clk) begin
hsync <= sync_pol ^ (vga_on ? hs_vga : hs); hsync <= hs;
vsync <= sync_pol ^ vs; vsync <= vs;
csync <= ~(vs ^ hs);
end end
endmodule endmodule

51
src/video/video_top.v
View File

@ -20,7 +20,6 @@ module video_top
// video syncs // video syncs
output wire hsync, output wire hsync,
output wire vsync, output wire vsync,
output wire csync,
output wire hblank, output wire hblank,
output wire vblank, output wire vblank,
output wire pix_stb, output wire pix_stb,
@ -80,12 +79,7 @@ module video_top
input wire ts_next, input wire ts_next,
output wire [20:0] tm_addr, output wire [20:0] tm_addr,
output wire tm_req, output wire tm_req,
input wire tm_next, input wire tm_next
// video controls
input wire cfg_60hz,
input wire sync_pol,
input wire vga_on
); );
@ -119,15 +113,11 @@ wire [9:0] x_offs_mode;
wire [4:0] go_offs; wire [4:0] go_offs;
wire [1:0] render_mode; wire [1:0] render_mode;
wire tv_hires; wire tv_hires;
wire vga_hires;
wire v60hz;
wire nogfx = vconf[5]; wire nogfx = vconf[5];
wire notsu = vconf[4]; wire notsu = vconf[4];
wire gfxovr = vconf[3]; wire gfxovr = vconf[3];
wire tv_hblank; wire tv_hblank;
wire tv_vblank; wire tv_vblank;
wire vga_hblank;
wire vga_vblank;
// counters // counters
wire [7:0] cnt_col; wire [7:0] cnt_col;
@ -140,7 +130,6 @@ wire [8:0] lcount;
wire frame_start; wire frame_start;
wire pix_start; wire pix_start;
wire tv_pix_start; wire tv_pix_start;
wire vga_pix_start;
wire ts_start; wire ts_start;
wire v_ts; wire v_ts;
wire v_pf; wire v_pf;
@ -160,7 +149,6 @@ wire fetch_stb;
// video data // video data
wire [7:0] border; wire [7:0] border;
wire [7:0] vplex; wire [7:0] vplex;
wire [7:0] vgaplex;
// TS // TS
wire tsr_go; wire tsr_go;
@ -179,10 +167,6 @@ wire [7:0] ts_wdata;
wire ts_we; wire ts_we;
wire [8:0] ts_raddr; wire [8:0] ts_raddr;
// VGA-line
wire [9:0] vga_cnt_in;
wire [9:0] vga_cnt_out;
video_ports video_ports video_ports video_ports
( (
.clk (clk), .clk (clk),
@ -243,7 +227,6 @@ video_mode video_mode
.c3 (c3), .c3 (c3),
.vpage (vpage), .vpage (vpage),
.vconf (vconf), .vconf (vconf),
.v60hz (v60hz),
.fetch_sel (fetch_sel), .fetch_sel (fetch_sel),
.fetch_bsl (fetch_bsl), .fetch_bsl (fetch_bsl),
.fetch_cnt (scnt), .fetch_cnt (scnt),
@ -268,7 +251,6 @@ video_mode video_mode
.line_start_s (line_start_s), .line_start_s (line_start_s),
.pix_start (pix_start), .pix_start (pix_start),
.tv_hires (tv_hires), .tv_hires (tv_hires),
.vga_hires (vga_hires),
.pix_stb (pix_stb), .pix_stb (pix_stb),
.render_mode (render_mode), .render_mode (render_mode),
.video_addr (video_addr), .video_addr (video_addr),
@ -299,13 +281,8 @@ video_sync video_sync
.vint_beg (vint_beg), .vint_beg (vint_beg),
.hsync (hsync), .hsync (hsync),
.vsync (vsync), .vsync (vsync),
.csync (csync),
.tv_hblank (tv_hblank), .tv_hblank (tv_hblank),
.tv_vblank (tv_vblank), .tv_vblank (tv_vblank),
.vga_hblank (vga_hblank),
.vga_vblank (vga_vblank),
.vga_cnt_in (vga_cnt_in),
.vga_cnt_out (vga_cnt_out),
.ts_raddr (ts_raddr), .ts_raddr (ts_raddr),
.lcount (lcount), .lcount (lcount),
.cnt_col (cnt_col), .cnt_col (cnt_col),
@ -327,10 +304,6 @@ video_sync video_sync
.hvpix (hvpix), .hvpix (hvpix),
.hvtspix (hvtspix), .hvtspix (hvtspix),
.nogfx (nogfx), .nogfx (nogfx),
.cfg_60hz (cfg_60hz),
.sync_pol (sync_pol),
.v60hz (v60hz),
.vga_on (vga_on),
.video_go (video_go), .video_go (video_go),
.video_pre_next(video_pre_next) .video_pre_next(video_pre_next)
); );
@ -440,28 +413,23 @@ video_render video_render
video_out video_out video_out video_out
( (
.clk (clk), .clk (clk),
.f0 (f0),
.c3 (c3), .c3 (c3),
.vga_on (vga_on),
.tv_blank (tv_hblank|tv_vblank), .tv_blank (tv_hblank|tv_vblank),
.vga_blank (vga_hblank|vga_vblank),
.palsel (palsel[3:0]), .palsel (palsel[3:0]),
.plex_sel_in ({h1, f1}), .plex_sel_in ({h1, f1}),
.tv_hires (tv_hires), .tv_hires (tv_hires),
.vga_hires (vga_hires),
.cram_addr_in (zma), .cram_addr_in (zma),
.cram_data_in (zmd[15:0]), .cram_data_in (zmd[15:0]),
.cram_we (cram_we), .cram_we (cram_we),
.vplex_in (vplex), .vplex_in (vplex),
.vgaplex (vgaplex),
.vred (vred), .vred (vred),
.vgrn (vgrn), .vgrn (vgrn),
.vblu (vblu), .vblu (vblu),
.vdac_mode (vdac_mode) .vdac_mode (vdac_mode)
); );
assign hblank = vga_on ? vga_hblank : tv_hblank; assign hblank = tv_hblank;
assign vblank = vga_on ? vga_vblank : tv_vblank; assign vblank = tv_vblank;
// 2 buffers: 512 pixels * 8 bits (9x8) - used as bitmap buffer for TS overlay over graphics // 2 buffers: 512 pixels * 8 bits (9x8) - used as bitmap buffer for TS overlay over graphics
// (2 altdprams) // (2 altdprams)
@ -496,17 +464,4 @@ dpram #(.ADDRWIDTH(9)) video_tsline1
.q_b (ts_rdata1) .q_b (ts_rdata1)
); );
// 2 lines * 512 pix * 8 bit (10x8) - used for VGA doubler
// (1 altdpram)
dpram #(.ADDRWIDTH(10)) video_vmem
(
.clock (clk),
.address_a (vga_cnt_in),
.data_a (vplex),
.wren_a (c3),
.address_b (vga_cnt_out),
.q_b (vgaplex)
);
endmodule endmodule