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https://github.com/UzixLS/TSConf_MiST.git
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Update sys. Re-organize the sources.
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sorgelig
403
rtl/sound/saa1099.sv
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403
rtl/sound/saa1099.sv
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//============================================================================
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//
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// SAA1099 sound generator
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// Copyright (C) 2016 Sorgelig
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//
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// Based on SAA1099.v code from Miguel Angel Rodriguez Jodar
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// Based on SAASound code from Dave Hooper
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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`timescale 1ns / 1ps
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`default_nettype none
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module saa1099
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(
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input clk_sys,
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input ce, // 8 MHz
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input rst_n,
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input cs_n,
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input a0, // 0=data, 1=address
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input wr_n,
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input [7:0] din,
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output [7:0] out_l,
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output [7:0] out_r
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);
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reg [7:0] amplit0, amplit1, amplit2, amplit3, amplit4, amplit5;
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reg [7:0] freq0, freq1, freq2, freq3, freq4, freq5;
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reg [7:0] oct10, oct32, oct54;
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reg [7:0] freqenable;
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reg [7:0] noiseenable;
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reg [7:0] noisegen;
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reg [7:0] envelope0, envelope1;
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reg [7:0] ctrl;
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reg [4:0] addr;
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wire rst = ~rst_n | ctrl[1];
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reg wr;
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always @(posedge clk_sys) begin
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reg old_wr;
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old_wr <= wr_n;
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wr <= 0;
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if(~rst_n) begin
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addr <= 0;
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{amplit0, amplit1, amplit2, amplit3, amplit4, amplit5} <= 0;
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{freq0, freq1, freq2, freq3, freq4, freq5} <= 0;
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{oct10, oct32, oct54} <= 0;
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{freqenable, noiseenable, noisegen} <= 0;
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{envelope0, envelope1} <= 0;
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ctrl <= 0;
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end
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else begin
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if(!cs_n & old_wr & !wr_n) begin
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wr <= 1;
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if(a0) addr <= din[4:0];
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else begin
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case (addr)
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'h00: amplit0 <= din;
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'h01: amplit1 <= din;
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'h02: amplit2 <= din;
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'h03: amplit3 <= din;
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'h04: amplit4 <= din;
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'h05: amplit5 <= din;
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'h08: freq0 <= din;
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'h09: freq1 <= din;
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'h0A: freq2 <= din;
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'h0B: freq3 <= din;
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'h0C: freq4 <= din;
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'h0D: freq5 <= din;
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'h10: oct10 <= din;
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'h11: oct32 <= din;
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'h12: oct54 <= din;
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'h14: freqenable <= din;
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'h15: noiseenable<= din;
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'h16: noisegen <= din;
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'h18: envelope0 <= din;
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'h19: envelope1 <= din;
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'h1C: ctrl <= din;
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endcase
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end
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end
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end
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end
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wire [21:0] out0;
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saa1099_triplet top
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(
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.*,
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.vol('{amplit0, amplit1, amplit2}),
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.env(envelope0),
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.freq('{freq0, freq1, freq2}),
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.octave('{oct10[2:0], oct10[6:4], oct32[2:0]}),
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.freq_en(freqenable[2:0]),
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.noise_en(noiseenable[2:0]),
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.noise_freq(noisegen[1:0]),
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.wr_addr(wr & a0 & (din[4:0] == 'h18)),
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.wr_data(wr & !a0 & (addr == 'h18)),
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.out(out0)
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);
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wire [21:0] out1;
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saa1099_triplet bottom
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(
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.*,
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.vol('{amplit3, amplit4, amplit5}),
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.env(envelope1),
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.freq('{freq3, freq4, freq5}),
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.octave('{oct32[6:4], oct54[2:0], oct54[6:4]}),
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.freq_en(freqenable[5:3]),
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.noise_en(noiseenable[5:3]),
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.noise_freq(noisegen[5:4]),
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.wr_addr(wr & a0 & (din[4:0] == 'h19)),
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.wr_data(wr & !a0 & (addr == 'h19)),
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.out(out1)
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);
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saa1099_output_mixer outmix_l(.*, .en(ctrl[0]), .in0(out0[10:0]), .in1(out1[10:0]), .out(out_l));
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saa1099_output_mixer outmix_r(.*, .en(ctrl[0]), .in0(out0[21:11]), .in1(out1[21:11]), .out(out_r));
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endmodule
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/////////////////////////////////////////////////////////////////////////////////
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module saa1099_triplet
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(
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input rst,
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input clk_sys,
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input ce,
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input [7:0] vol[3],
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input [7:0] env,
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input [7:0] freq[3],
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input [2:0] octave[3],
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input [2:0] freq_en,
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input [2:0] noise_en,
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input [1:0] noise_freq,
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input wr_addr,
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input wr_data,
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output[21:0] out
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);
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wire tone0, tone1, tone2, noise;
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wire pulse_noise, pulse_envelope;
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wire[21:0] out0, out1, out2;
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saa1099_tone freq_gen0(.*, .out(tone0), .octave(octave[0]), .freq(freq[0]), .pulse(pulse_noise));
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saa1099_tone freq_gen1(.*, .out(tone1), .octave(octave[1]), .freq(freq[1]), .pulse(pulse_envelope));
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saa1099_tone freq_gen2(.*, .out(tone2), .octave(octave[2]), .freq(freq[2]), .pulse());
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saa1099_noise noise_gen(.*, .out(noise));
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saa1099_amp amp0(.*, .mixmode({noise_en[0], freq_en[0]}), .tone(tone0), .envreg(0), .vol(vol[0]), .out(out0));
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saa1099_amp amp1(.*, .mixmode({noise_en[1], freq_en[1]}), .tone(tone1), .envreg(0), .vol(vol[1]), .out(out1));
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saa1099_amp amp2(.*, .mixmode({noise_en[2], freq_en[2]}), .tone(tone2), .envreg(env), .vol(vol[2]), .out(out2));
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assign out[10:0] = out0[8:0] + out1[8:0] + out2[8:0];
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assign out[21:11] = out0[17:9] + out1[17:9] + out2[17:9];
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endmodule
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/////////////////////////////////////////////////////////////////////////////////
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module saa1099_tone
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(
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input rst,
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input clk_sys,
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input ce,
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input [2:0] octave,
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input [7:0] freq,
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output reg out,
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output reg pulse
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);
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wire [16:0] fcount = ((17'd511 - freq) << (4'd8 - octave)) - 1'd1;
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always @(posedge clk_sys) begin
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reg [16:0] count;
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pulse <= 0;
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if(rst) begin
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count <= fcount;
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out <= 0;
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end else if(ce) begin
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if(!count) begin
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count <= fcount;
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pulse <= 1;
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out <= ~out;
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end else begin
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count <= count - 1'd1;
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end
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end
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end
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endmodule
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/////////////////////////////////////////////////////////////////////////////////
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module saa1099_noise
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(
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input rst,
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input clk_sys,
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input ce,
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input pulse_noise,
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input [1:0] noise_freq,
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output out
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);
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reg [16:0] lfsr = 0;
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wire [16:0] new_lfsr = {(lfsr[0] ^ lfsr[2] ^ !lfsr), lfsr[16:1]};
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wire [10:0] fcount = (11'd256 << noise_freq) - 1'b1;
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always @(posedge clk_sys) begin
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reg [10:0] count;
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if(rst) begin
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count <= fcount;
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end else
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if(noise_freq != 3) begin
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if(ce) begin
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if(!count) begin
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count <= fcount;
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lfsr <= new_lfsr;
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end else begin
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count <= count - 1'd1;
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end
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end
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end else if(pulse_noise) begin
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lfsr <= new_lfsr;
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end
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end
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assign out = lfsr[0];
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endmodule
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/////////////////////////////////////////////////////////////////////////////////
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module saa1099_amp
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(
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input rst,
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input clk_sys,
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input [7:0] envreg,
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input [1:0] mixmode,
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input tone,
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input noise,
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input wr_addr,
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input wr_data,
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input pulse_envelope,
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input [7:0] vol,
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output reg [17:0] out
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);
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wire phases[8] = '{0,0,0,0,1,1,0,0};
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wire [1:0] env[8][2] = '{'{0,0}, '{1,1}, '{2,0}, '{2,0}, '{3,2}, '{3,2}, '{3,0}, '{3,0}};
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wire [3:0] levels[4][16] =
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'{
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'{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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'{15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15},
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'{15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0},
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'{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15}
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};
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reg [2:0] shape;
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reg stereo;
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wire resolution = envreg[4];
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wire enable = envreg[7];
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reg [3:0] counter;
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reg phase;
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wire[3:0] mask = {3'b000, resolution};
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always @(posedge clk_sys) begin
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reg clock;
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reg new_data;
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if(rst | ~enable) begin
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new_data <= 0;
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stereo <= envreg[0];
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shape <= envreg[3:1];
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clock <= envreg[5];
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phase <= 0;
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counter <= 0;
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end
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else begin
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if(wr_data) new_data <= 1;
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if(clock ? wr_addr : pulse_envelope) begin // pulse from internal or external clock?
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counter <= counter + resolution + 1'd1;
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if((counter | mask) == 15) begin
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if(phase >= phases[shape]) begin
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if(~shape[0]) counter <= 15;
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if(new_data | shape[0]) begin // if we reached one of the designated points (3) or (4) and there is pending data, load it
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new_data <= 0;
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stereo <= envreg[0];
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shape <= envreg[3:1];
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clock <= envreg[5];
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phase <= 0;
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if(new_data) counter <= 0;
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end
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end else begin
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phase <= 1;
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end
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end
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end
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end
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end
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wire [3:0] env_l = levels[env[shape][phase]][counter] & ~mask;
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wire [3:0] env_r = stereo ? (4'd15 & ~mask) - env_l : env_l; // bit 0 of envreg inverts envelope shape
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reg [1:0] outmix;
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always_comb begin
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case(mixmode)
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0: outmix <= 0;
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1: outmix <= {tone, 1'b0};
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2: outmix <= {noise, 1'b0};
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3: outmix <= {tone & ~noise, tone & noise};
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endcase
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end
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wire [8:0] vol_mix_l = {vol[3:1], vol[0] & ~enable, 5'b00000} >> outmix[0];
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wire [8:0] vol_mix_r = {vol[7:5], vol[4] & ~enable, 5'b00000} >> outmix[0];
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wire [8:0] env_out_l;
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wire [8:0] env_out_r;
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saa1099_mul_env mod_l(.vol(vol_mix_l[8:4]), .env(env_l), .out(env_out_l));
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saa1099_mul_env mod_r(.vol(vol_mix_r[8:4]), .env(env_r), .out(env_out_r));
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always_comb begin
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case({enable, outmix})
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'b100, 'b101: out = {env_out_r, env_out_l};
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'b001, 'b010: out = {vol_mix_r, vol_mix_l};
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default: out = 0;
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endcase
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end
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endmodule
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/////////////////////////////////////////////////////////////////////////////////
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module saa1099_mul_env
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(
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input [4:0] vol,
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input [3:0] env,
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output [8:0] out
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);
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assign out = (env[0] ? vol : 9'd0)+
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(env[1] ? { vol,1'b0} : 9'd0)+
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(env[2] ? { vol,2'b00} : 9'd0)+
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(env[3] ? {vol,3'b000} : 9'd0);
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endmodule
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/////////////////////////////////////////////////////////////////////////////////
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module saa1099_output_mixer
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(
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input clk_sys,
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input ce,
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input en,
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input [10:0] in0,
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input [10:0] in1,
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output reg [7:0] out
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);
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wire [17:0] o = 18'd91 * ({1'b0,in0} + {1'b0,in1});
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// Clean the audio.
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always @(posedge clk_sys) begin
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reg ced;
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ced <= ce;
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if(ced) out <= ~en ? 8'h00 : o[17:10];
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end
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endmodule
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Block a user