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https://github.com/UzixLS/TSConf_MiST.git
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Update sys. Re-organize the sources.
This commit is contained in:
sorgelig
412
rtl/sound/jt12/jt12_pg.v
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412
rtl/sound/jt12/jt12_pg.v
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/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2016
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Based on information posted by Nemesis on:
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http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
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Based on jt51_phasegen.v, from JT51
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*/
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`timescale 1ns / 1ps
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/*
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tab size 4
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*/
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module jt12_pg(
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input clk,
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input rst,
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// Channel frequency
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input [10:0] fnum_I,
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input [ 2:0] block_I,
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// Operator multiplying
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input [ 3:0] mul_V,
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// Operator detuning
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input [ 2:0] dt1_II, // same as JT51's DT1
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// phase modulation from LFO
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//input [ 7:0] pm,
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//input [ 2:0] pms,
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// phase operation
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input pg_rst_III,
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input zero,
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input pg_stop,
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output reg [ 4:0] keycode_III,
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output reg [ 9:0] phase_VIII
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);
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/*
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reg signed [8:0] mod;
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always @(*) begin
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case( pms ) // comprobar en silicio
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3'd0: mod <= 9'd0;
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3'd1: mod <= { 7'd0, pm[6:5] };
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3'd2: mod <= { 6'd0, pm[6:4] };
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3'd3: mod <= { 5'd0, pm[6:3] };
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3'd4: mod <= { 4'd0, pm[6:2] };
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3'd5: mod <= { 3'd0, pm[6:1] };
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3'd6: mod <= { 1'd0, pm[6:0], 1'b0 };
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3'd7: mod <= { pm[6:0], 2'b0 };
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endcase
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end
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jt12_pm u_pm(
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// Channel frequency
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.kc(kc),
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.kf(kf),
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.add(~pm[7]),
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.mod(mod),
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.kcex(keycode_I)
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);
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*/
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wire pg_rst_VI;
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//////////////////////////////////////////////////
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// I
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reg [4:0] keycode_II;
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reg [16:0] phinc_II;
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always @(posedge clk) begin : phase_calculation_I
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case ( block_I )
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3'd0: phinc_II <= { 7'd0, fnum_I[10:1] };
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3'd1: phinc_II <= { 6'd0, fnum_I };
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3'd2: phinc_II <= { 5'd0, fnum_I, 1'd0 };
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3'd3: phinc_II <= { 4'd0, fnum_I, 2'd0 };
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3'd4: phinc_II <= { 3'd0, fnum_I, 3'd0 };
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3'd5: phinc_II <= { 2'd0, fnum_I, 4'd0 };
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3'd6: phinc_II <= { 1'd0, fnum_I, 5'd0 };
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3'd7: phinc_II <= { fnum_I, 6'd0 };
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endcase
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keycode_II <= { block_I, fnum_I[10], fnum_I[10] ? (|fnum_I[9:7]) : (&fnum_I[9:7])};
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end
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//////////////////////////////////////////////////
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// II
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reg [ 5:0] dt1_kf_III;
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reg [16:0] phinc_III;
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reg [ 2:0] dt1_III;
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always @(posedge clk) begin : phase_calculation_II
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case( dt1_II[1:0] )
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2'd1: dt1_kf_III <= { 1'b0, keycode_II } - 6'd4;
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2'd2: dt1_kf_III <= { 1'b0, keycode_II } + 6'd4;
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2'd3: dt1_kf_III <= { 1'b0, keycode_II } + 6'd8;
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default:dt1_kf_III <= { 1'b0, keycode_II };
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endcase
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dt1_III <= dt1_II;
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phinc_III <= phinc_II;
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keycode_III <= keycode_II;
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end
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//////////////////////////////////////////////////
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// III
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reg [16:0] phinc_IV;
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reg [ 4:0] pow2;
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reg [ 2:0] dt1_IV;
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always @(*) begin : calcpow2
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case( dt1_kf_III[2:0] )
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3'd0: pow2 <= 5'd16;
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3'd1: pow2 <= 5'd17;
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3'd2: pow2 <= 5'd19;
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3'd3: pow2 <= 5'd20;
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3'd4: pow2 <= 5'd22;
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3'd5: pow2 <= 5'd24;
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3'd6: pow2 <= 5'd26;
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3'd7: pow2 <= 5'd29;
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endcase
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end
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reg [5:0] dt1_unlimited;
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reg [4:0] dt1_limit, dt1_offset_IV;
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always @(*) begin : dt1_limit_mux
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case( dt1_III[1:0] )
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default: dt1_limit <= 5'd8;
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2'd1: dt1_limit <= 5'd8;
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2'd2: dt1_limit <= 5'd16;
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2'd3: dt1_limit <= 5'd22;
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endcase
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case( dt1_kf_III[5:3] )
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3'd0: dt1_unlimited <= { 5'd0, pow2[4] }; // <2
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3'd1: dt1_unlimited <= { 4'd0, pow2[4:3] }; // <4
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3'd2: dt1_unlimited <= { 3'd0, pow2[4:2] }; // <8
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3'd3: dt1_unlimited <= { 2'd0, pow2[4:1] };
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3'd4: dt1_unlimited <= { 1'd0, pow2[4:0] };
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3'd5: dt1_unlimited <= { pow2[4:0], 1'd0 };
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default:dt1_unlimited <= 6'd0;
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endcase
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end
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always @(posedge clk) begin : phase_calculation_III
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dt1_offset_IV <= dt1_unlimited > dt1_limit ?
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dt1_limit : dt1_unlimited[4:0];
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dt1_IV <= dt1_III;
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phinc_IV <= phinc_III;
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end
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//////////////////////////////////////////////////
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// IV
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reg [16:0] phinc_V;
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always @(posedge clk) begin : phase_calculation_IV
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if( dt1_IV[1:0]==2'd0 )
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phinc_V <= phinc_IV;
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else begin
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if( !dt1_IV[2] )
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phinc_V <= phinc_IV + dt1_offset_IV;
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else
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phinc_V <= phinc_IV - dt1_offset_IV;
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end
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end
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//////////////////////////////////////////////////
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// V APPLY_MUL
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reg [16:0] phinc_VI;
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always @(posedge clk) begin : phase_calculation_V
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if( mul_V==4'd0 )
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phinc_VI <= { 1'b0, phinc_V[16:1] };
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else
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phinc_VI <= phinc_V * mul_V;
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end
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//////////////////////////////////////////////////
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// VI add phinc to the phase
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wire keyon_VI;
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wire [19:0] phase_drop;
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reg [19:0] phase_in;
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reg [ 9:0] phase_VII;
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always @(*)
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phase_in <= pg_rst_VI ? 20'd0 :
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( pg_stop ? phase_drop : phase_drop + phinc_VI);
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always @(posedge clk) begin : phase_calculation_VI
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phase_VII <= phase_in[19:10];
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end
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//////////////////////////////////////////////////
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// VIII padding
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always @(posedge clk)
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phase_VIII <= phase_VII;
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jt12_sh #( .width(20), .stages(24) ) u_phsh(
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.clk ( clk ),
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// .rst ( rst ),
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.din ( phase_in ),
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.drop ( phase_drop)
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);
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jt12_sh #( .width(1), .stages(3) ) u_rstsh(
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.clk ( clk ),
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.din ( pg_rst_III),
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.drop ( pg_rst_VI )
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);
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`ifdef SIMULATION
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reg [4:0] sep24_cnt;
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wire [9:0] pg_ch0s1, pg_ch1s1, pg_ch2s1, pg_ch3s1,
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pg_ch4s1, pg_ch5s1, pg_ch0s2, pg_ch1s2,
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pg_ch2s2, pg_ch3s2, pg_ch4s2, pg_ch5s2,
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pg_ch0s3, pg_ch1s3, pg_ch2s3, pg_ch3s3,
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pg_ch4s3, pg_ch5s3, pg_ch0s4, pg_ch1s4,
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pg_ch2s4, pg_ch3s4, pg_ch4s4, pg_ch5s4;
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always @(posedge clk)
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sep24_cnt <= !zero ? sep24_cnt+1'b1 : 5'd0;
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sep24 #( .width(10), .pos0(18)) stsep
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(
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.clk ( clk ),
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.mixed ( phase_VIII),
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.mask ( 0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (pg_ch0s1),
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.ch1s1 (pg_ch1s1),
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.ch2s1 (pg_ch2s1),
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.ch3s1 (pg_ch3s1),
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.ch4s1 (pg_ch4s1),
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.ch5s1 (pg_ch5s1),
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.ch0s2 (pg_ch0s2),
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.ch1s2 (pg_ch1s2),
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.ch2s2 (pg_ch2s2),
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.ch3s2 (pg_ch3s2),
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.ch4s2 (pg_ch4s2),
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.ch5s2 (pg_ch5s2),
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.ch0s3 (pg_ch0s3),
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.ch1s3 (pg_ch1s3),
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.ch2s3 (pg_ch2s3),
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.ch3s3 (pg_ch3s3),
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.ch4s3 (pg_ch4s3),
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.ch5s3 (pg_ch5s3),
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.ch0s4 (pg_ch0s4),
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.ch1s4 (pg_ch1s4),
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.ch2s4 (pg_ch2s4),
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.ch3s4 (pg_ch3s4),
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.ch4s4 (pg_ch4s4),
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.ch5s4 (pg_ch5s4)
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);
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wire [16:0] phinc_ch0s1, phinc_ch1s1, phinc_ch2s1, phinc_ch3s1,
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phinc_ch4s1, phinc_ch5s1, phinc_ch0s2, phinc_ch1s2,
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phinc_ch2s2, phinc_ch3s2, phinc_ch4s2, phinc_ch5s2,
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phinc_ch0s3, phinc_ch1s3, phinc_ch2s3, phinc_ch3s3,
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phinc_ch4s3, phinc_ch5s3, phinc_ch0s4, phinc_ch1s4,
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phinc_ch2s4, phinc_ch3s4, phinc_ch4s4, phinc_ch5s4;
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sep24 #( .width(17), .pos0(3+6)) pisep
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(
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.clk ( clk ),
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.mixed ( phinc_VI),
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.mask ( 0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (phinc_ch0s1),
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.ch1s1 (phinc_ch1s1),
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.ch2s1 (phinc_ch2s1),
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.ch3s1 (phinc_ch3s1),
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.ch4s1 (phinc_ch4s1),
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.ch5s1 (phinc_ch5s1),
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.ch0s2 (phinc_ch0s2),
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.ch1s2 (phinc_ch1s2),
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.ch2s2 (phinc_ch2s2),
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.ch3s2 (phinc_ch3s2),
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.ch4s2 (phinc_ch4s2),
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.ch5s2 (phinc_ch5s2),
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.ch0s3 (phinc_ch0s3),
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.ch1s3 (phinc_ch1s3),
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.ch2s3 (phinc_ch2s3),
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.ch3s3 (phinc_ch3s3),
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.ch4s3 (phinc_ch4s3),
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.ch5s3 (phinc_ch5s3),
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.ch0s4 (phinc_ch0s4),
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.ch1s4 (phinc_ch1s4),
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.ch2s4 (phinc_ch2s4),
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.ch3s4 (phinc_ch3s4),
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.ch4s4 (phinc_ch4s4),
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.ch5s4 (phinc_ch5s4)
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);
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wire [10:0] fnum_ch0s1, fnum_ch1s1, fnum_ch2s1, fnum_ch3s1,
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fnum_ch4s1, fnum_ch5s1, fnum_ch0s2, fnum_ch1s2,
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fnum_ch2s2, fnum_ch3s2, fnum_ch4s2, fnum_ch5s2,
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fnum_ch0s3, fnum_ch1s3, fnum_ch2s3, fnum_ch3s3,
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fnum_ch4s3, fnum_ch5s3, fnum_ch0s4, fnum_ch1s4,
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fnum_ch2s4, fnum_ch3s4, fnum_ch4s4, fnum_ch5s4;
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sep24 #( .width(11), .pos0(3+1)) fnsep
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(
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.clk ( clk ),
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.mixed ( fnum_I),
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.mask ( 0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (fnum_ch0s1),
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.ch1s1 (fnum_ch1s1),
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.ch2s1 (fnum_ch2s1),
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.ch3s1 (fnum_ch3s1),
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.ch4s1 (fnum_ch4s1),
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.ch5s1 (fnum_ch5s1),
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.ch0s2 (fnum_ch0s2),
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.ch1s2 (fnum_ch1s2),
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.ch2s2 (fnum_ch2s2),
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.ch3s2 (fnum_ch3s2),
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.ch4s2 (fnum_ch4s2),
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.ch5s2 (fnum_ch5s2),
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.ch0s3 (fnum_ch0s3),
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.ch1s3 (fnum_ch1s3),
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.ch2s3 (fnum_ch2s3),
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.ch3s3 (fnum_ch3s3),
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.ch4s3 (fnum_ch4s3),
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.ch5s3 (fnum_ch5s3),
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.ch0s4 (fnum_ch0s4),
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.ch1s4 (fnum_ch1s4),
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.ch2s4 (fnum_ch2s4),
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.ch3s4 (fnum_ch3s4),
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.ch4s4 (fnum_ch4s4),
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.ch5s4 (fnum_ch5s4)
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);
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wire pgrst_III_ch0s1, pgrst_III_ch1s1, pgrst_III_ch2s1, pgrst_III_ch3s1,
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pgrst_III_ch4s1, pgrst_III_ch5s1, pgrst_III_ch0s2, pgrst_III_ch1s2,
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pgrst_III_ch2s2, pgrst_III_ch3s2, pgrst_III_ch4s2, pgrst_III_ch5s2,
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pgrst_III_ch0s3, pgrst_III_ch1s3, pgrst_III_ch2s3, pgrst_III_ch3s3,
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pgrst_III_ch4s3, pgrst_III_ch5s3, pgrst_III_ch0s4, pgrst_III_ch1s4,
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pgrst_III_ch2s4, pgrst_III_ch3s4, pgrst_III_ch4s4, pgrst_III_ch5s4;
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sep24 #( .width(1), .pos0(23)) pgrstsep
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(
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.clk ( clk ),
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.mixed ( pg_rst_III),
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.mask ( 0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (pgrst_III_ch0s1),
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.ch1s1 (pgrst_III_ch1s1),
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.ch2s1 (pgrst_III_ch2s1),
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.ch3s1 (pgrst_III_ch3s1),
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.ch4s1 (pgrst_III_ch4s1),
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.ch5s1 (pgrst_III_ch5s1),
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.ch0s2 (pgrst_III_ch0s2),
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.ch1s2 (pgrst_III_ch1s2),
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.ch2s2 (pgrst_III_ch2s2),
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.ch3s2 (pgrst_III_ch3s2),
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.ch4s2 (pgrst_III_ch4s2),
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.ch5s2 (pgrst_III_ch5s2),
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.ch0s3 (pgrst_III_ch0s3),
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.ch1s3 (pgrst_III_ch1s3),
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.ch2s3 (pgrst_III_ch2s3),
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.ch3s3 (pgrst_III_ch3s3),
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.ch4s3 (pgrst_III_ch4s3),
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.ch5s3 (pgrst_III_ch5s3),
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.ch0s4 (pgrst_III_ch0s4),
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.ch1s4 (pgrst_III_ch1s4),
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.ch2s4 (pgrst_III_ch2s4),
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.ch3s4 (pgrst_III_ch3s4),
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.ch4s4 (pgrst_III_ch4s4),
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.ch5s4 (pgrst_III_ch5s4)
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);
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`endif
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endmodule
|
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