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sorgelig
2019-03-07 20:55:56 +08:00
parent defa3b88ca
commit 55487f158b
40 changed files with 4945 additions and 8940 deletions
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128
sys/alsa.sv Normal file
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@ -0,0 +1,128 @@
//============================================================================
//
// ALSA sound support for MiSTer
// (c)2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module alsa
(
input reset,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
input spi_ss,
input spi_sck,
input spi_mosi,
output reg [15:0] pcm_l,
output reg [15:0] pcm_r
);
reg spi_new = 0;
reg [127:0] spi_data;
always @(posedge spi_sck, posedge spi_ss) begin
reg [7:0] mosi;
reg [6:0] spicnt = 0;
if(spi_ss) spicnt <= 0;
else begin
mosi <= {mosi[6:0],spi_mosi};
spicnt <= spicnt + 1'd1;
if(&spicnt[2:0]) begin
spi_data[{spicnt[6:3],3'b000} +:8] <= {mosi[6:0],spi_mosi};
spi_new <= &spicnt;
end
end
end
reg [31:0] buf_addr;
reg [31:0] buf_len;
reg [31:0] buf_wptr = 0;
always @(posedge ram_clk) begin
reg n1,n2,n3;
reg [127:0] data1,data2;
n1 <= spi_new;
n2 <= n1;
n3 <= n2;
data1 <= spi_data;
data2 <= data1;
if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
end
reg [31:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg got_first = 0;
reg ready = 0;
reg ud;
reg [31:0] readdata;
if(~ram_waitrequest) ram_read <= 0;
if(ram_readdatavalid && ram_burstcount) begin
ram_burstcount <= 0;
ready <= 1;
readdata <= ud ? ram_readdata[63:32] : ram_readdata[31:0];
if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
end
if(reset) {ready, got_first} <= 0;
else
if(buf_rptr[31:2] != buf_wptr[31:2]) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else
if(!ram_burstcount && ~ram_waitrequest && ~ready) begin
ram_address <= buf_addr[31:3] + buf_rptr[31:3];
ud <= buf_rptr[2];
ram_burstcount <= 1;
ram_read <= 1;
buf_rptr <= buf_rptr + 4;
end
end
if(ready & ce_48k) begin
{pcm_r,pcm_l} <= readdata;
ready <= 0;
end
end
reg ce_48k;
always @(posedge ram_clk) begin
reg [15:0] acc = 0;
ce_48k <= 0;
acc <= acc + 16'd48;
if(acc >= 50000) begin
acc <= acc - 16'd50000;
ce_48k <= 1;
end
end
endmodule

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sys/ascal.vhd Normal file
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157
sys/audio_out.v Normal file
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module audio_out
#(
parameter CLK_RATE = 50000000
)
(
input reset,
input clk,
//0 - 48KHz, 1 - 96KHz
input sample_rate,
input [15:0] left_in,
input [15:0] right_in,
// I2S
output i2s_bclk,
output i2s_lrclk,
output i2s_data,
// SPDIF
output spdif,
// Sigma-Delta DAC
output dac_l,
output dac_r
);
localparam AUDIO_RATE = 48000;
localparam AUDIO_DW = 16;
localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;
wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];
reg mclk_ce;
always @(posedge clk) begin
reg [31:0] cnt;
mclk_ce <= 0;
cnt = cnt + real_ce;
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
mclk_ce <= 1;
end
end
reg i2s_ce;
always @(posedge clk) begin
reg div;
i2s_ce <= 0;
if(mclk_ce) begin
div <= ~div;
i2s_ce <= div;
end
end
reg lpf_ce;
always @(posedge clk) begin
integer div;
lpf_ce <= 0;
if(mclk_ce) begin
div <= div + 1;
if(div == FILTER_DIV) begin
div <= 0;
lpf_ce <= 1;
end
end
end
i2s i2s
(
.reset(reset),
.clk(clk),
.ce(i2s_ce),
.sclk(i2s_bclk),
.lrclk(i2s_lrclk),
.sdata(i2s_data),
.left_chan(al),
.right_chan(ar)
);
spdif toslink
(
.rst_i(reset),
.clk_i(clk),
.bit_out_en_i(mclk_ce),
.sample_i({ar,al}),
.spdif_o(spdif)
);
sigma_delta_dac #(15) sd_l
(
.CLK(clk),
.RESET(reset),
.DACin({~al[15], al[14:0]}),
.DACout(dac_l)
);
sigma_delta_dac #(15) sd_r
(
.CLK(clk),
.RESET(reset),
.DACin({~ar[15], ar[14:0]}),
.DACout(dac_r)
);
wire [15:0] al, ar;
lpf_aud lpf_l
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(left_in),
.ODATA(al)
);
lpf_aud lpf_r
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(right_in),
.ODATA(ar)
);
endmodule
module lpf_aud
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule

4
sys/hdmi_config.sv
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@ -142,9 +142,9 @@ wire [15:0] init_data[58] =
16'hAA00, // ADI required Write.
16'hAB40, // ADI required Write.
{8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
{8'hAF, 6'b0000_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
// [6:5] must be b00!
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
// [4]=0 Current frame is unencrypted
// [3:2] must be b01!
// [1]=1 HDMI Mode.
// [0] must be b0!

395
sys/hdmi_lite.sv
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@ -1,395 +0,0 @@
//============================================================================
//
// HDMI Lite output module
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
//============================================================================
module hdmi_lite
(
input reset,
input clk_video,
input ce_pixel,
input video_vs,
input video_de,
input [23:0] video_d,
input clk_hdmi,
input hdmi_hde,
input hdmi_vde,
output reg hdmi_de,
output [23:0] hdmi_d,
input [11:0] screen_w,
input [11:0] screen_h,
input quadbuf,
// 0-3 => scale 1-4
input [1:0] scale_x,
input [1:0] scale_y,
input scale_auto,
input clk_vbuf,
output [27:0] vbuf_address,
input [127:0] vbuf_readdata,
output [127:0] vbuf_writedata,
output [7:0] vbuf_burstcount,
output [15:0] vbuf_byteenable,
input vbuf_waitrequest,
input vbuf_readdatavalid,
output reg vbuf_read,
output reg vbuf_write
);
localparam [7:0] burstsz = 64;
reg [1:0] nbuf = 0;
wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
wire [95:0] hf_out;
wire [7:0] hf_usedw;
reg hf_reset = 0;
vbuf_fifo out_fifo
(
.aclr(hf_reset),
.wrclk(clk_vbuf),
.wrreq(vbuf_readdatavalid),
.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
.wrusedw(hf_usedw),
.rdclk(~clk_hdmi),
.rdreq(hf_rdreq),
.q(hf_out)
);
reg [11:0] rd_stride;
wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
reg [27:0] vbuf_raddress;
reg [7:0] vbuf_rburstcount;
always @(posedge clk_vbuf) begin
reg [18:0] rdcnt;
reg [7:0] bcnt;
reg vde1, vde2;
reg [1:0] mcnt;
reg [1:0] my;
reg [18:0] fsz;
reg [11:0] strd;
vde1 <= hdmi_vde;
vde2 <= vde1;
if(vbuf_readdatavalid) begin
rdcnt <= rdcnt + 1'd1;
if(bcnt) bcnt <= bcnt - 1'd1;
vbuf_raddress <= vbuf_raddress + 1'd1;
end
if(!bcnt && reading) reading <= 0;
vbuf_read <= 0;
if(~vbuf_waitrequest) begin
if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
vbuf_read <= 1;
reading <= 1;
bcnt <= rd_burst;
vbuf_rburstcount <= rd_burst;
rd_stride <= rd_stride - rd_burst;
if(!(rd_stride - rd_burst)) rd_stride <= strd;
if(!rdcnt) begin
vbuf_raddress <= read_buf;
mcnt <= my;
end
else if (rd_stride == strd) begin
mcnt <= mcnt - 1'd1;
if(!mcnt) mcnt <= my;
else vbuf_raddress <= vbuf_raddress - strd;
end
end
end
hf_reset <= 0;
if(vde2 & ~vde1) begin
hf_reset <= 1;
rdcnt <= 0;
bcnt <= 0;
rd_stride <= stride;
strd <= stride;
fsz <= framesz;
my <= mult_y;
end
end
reg [11:0] off_x, off_y;
reg [11:0] x, y;
reg [11:0] vh_height;
reg [11:0] vh_width;
reg [1:0] pcnt;
reg [1:0] hload;
wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
wire de_in = hdmi_hde & hdmi_vde;
always @(posedge clk_hdmi) begin
reg [71:0] px_out;
reg [1:0] mx;
reg vde;
vde <= hdmi_vde;
if(vde & ~hdmi_vde) begin
off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
vh_height <= v_height;
vh_width <= v_width;
mx <= mult_x;
end
pcnt <= pcnt + 1'd1;
if(pcnt == mx) begin
pcnt <= 0;
hload <= hload + 1'd1;
end
if(~de_in || x<off_x || y<off_y) begin
hload <= 0;
pcnt <= 0;
end
hdmi_de <= de_in;
x <= x + 1'd1;
if(~hdmi_de & de_in) x <= 0;
if(hdmi_de & ~de_in) y <= y + 1'd1;
if(~hdmi_vde) y <= 0;
if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
end
//////////////////////////////////////////////////////////////////////////////
reg reading = 0;
reg writing = 0;
reg op_split = 0;
always @(posedge clk_vbuf) op_split <= ~op_split;
wire allow_rd = ~reading & ~writing & op_split & ~reset;
wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
//////////////////////////////////////////////////////////////////////////////
reg vf_rdreq = 0;
wire [95:0] vf_out;
assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
vbuf_fifo in_fifo
(
.aclr(video_vs),
.rdclk(clk_vbuf),
.rdreq(vf_rdreq & ~vbuf_waitrequest),
.q(vf_out),
.wrclk(clk_video),
.wrreq(infifo_wr),
.data({video_de ? video_d : 24'd0, pix_acc})
);
assign vbuf_byteenable = '1;
reg [35:0] addrque[3:0] = '{0,0,0,0};
reg [7:0] flush_size;
reg [27:0] flush_addr;
reg flush_req = 0;
reg flush_ack = 0;
reg [27:0] vbuf_waddress;
reg [7:0] vbuf_wburstcount;
always @(posedge clk_vbuf) begin
reg [7:0] ibcnt = 0;
reg reqd = 0;
reqd <= flush_req;
if(~vbuf_waitrequest) begin
vbuf_write <= vf_rdreq;
if(~vf_rdreq && writing) writing <= 0;
if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
ibcnt <= addrque[0][7:0];
addrque[0] <= addrque[1];
addrque[1] <= addrque[2];
addrque[2] <= addrque[3];
addrque[3] <= 0;
vf_rdreq <= 1;
writing <= 1;
end
else if(flush_ack != reqd) begin
if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
flush_ack <= reqd;
end
if(vf_rdreq) begin
if(ibcnt == 1) vf_rdreq <= 0;
ibcnt <= ibcnt - 1'd1;
end
end
end
reg [11:0] stride;
reg [18:0] framesz;
reg [11:0] v_height;
reg [11:0] v_width;
reg [1:0] mult_x;
reg [1:0] mult_y;
reg [71:0] pix_acc;
wire pix_wr = ce_pixel && video_de;
reg [27:0] cur_addr;
reg [11:0] video_x;
reg [11:0] video_y;
wire infifo_tail = ~video_de && video_x[1:0];
wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
wire [23:0] t_fsz = l1_stride * t_height;
reg [11:0] l1_width;
reg [11:0] l1_stride;
always @(posedge clk_video) begin
reg [7:0] loaded = 0;
reg [11:0] strd = 0;
reg old_de = 0;
reg old_vs = 0;
old_vs <= video_vs;
if(~old_vs & video_vs) begin
cur_addr<= write_buf;
video_x <= 0;
video_y <= 0;
loaded <= 0;
strd <= 0;
nbuf <= nbuf + 1'd1;
stride <= l1_stride;
framesz <= t_fsz[18:0];
v_height<= t_height;
v_width <= t_width;
mult_x <= tmf_x;
mult_y <= tmf_y;
end
if(pix_wr) begin
case(video_x[1:0])
0: pix_acc <= video_d; // zeroes upper bits too
1: pix_acc[47:24] <= video_d;
2: pix_acc[71:48] <= video_d;
3: loaded <= loaded + 1'd1;
endcase
if(video_x<screen_w) video_x <= video_x + 1'd1;
end
old_de <= video_de;
if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
if(loaded + infifo_tail) begin
flush_size <= loaded + infifo_tail;
flush_addr <= cur_addr;
flush_req <= ~flush_req;
loaded <= 0;
strd <= strd + loaded;
end
cur_addr <= cur_addr + loaded + infifo_tail;
if(~video_de) begin
if(video_y<screen_h) video_y <= video_y + 1'd1;
video_x <= 0;
strd <= 0;
// measure width by first line (same as VIP)
if(!video_y) begin
l1_width <= video_x;
l1_stride <= strd + loaded + infifo_tail;
end
end
end
end
endmodule
module vbuf_fifo
(
input aclr,
input rdclk,
input rdreq,
output [95:0] q,
input wrclk,
input wrreq,
input [95:0] data,
output [7:0] wrusedw
);
dcfifo dcfifo_component
(
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (q),
.wrusedw (wrusedw),
.eccstatus (),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 96,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule

135
sys/hps_io.v
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@ -40,14 +40,24 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
output reg [15:0] joystick_0,
output reg [15:0] joystick_1,
output reg [15:0] joystick_2,
output reg [15:0] joystick_3,
output reg [15:0] joystick_4,
output reg [15:0] joystick_5,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output reg [15:0] joystick_analog_2,
output reg [15:0] joystick_analog_3,
output reg [15:0] joystick_analog_4,
output reg [15:0] joystick_analog_5,
output [1:0] buttons,
output forced_scandoubler,
output reg [31:0] status,
input [31:0] status_in,
input status_set,
//toggle to force notify of video mode change
input new_vmode,
@ -61,7 +71,7 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
input [VD:0] sd_rd, // only single sd_rd can be active at any given time
input [VD:0] sd_wr, // only single sd_wr can be active at any given time
output reg sd_ack,
// do not use in new projects.
// CID and CSD are fake except CSD image size field.
input sd_conf,
@ -88,6 +98,9 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
// Seconds since 1970-01-01 00:00:00
output reg [32:0] TIMESTAMP,
// UART flags
input [15:0] uart_mode,
// ps2 keyboard emulation
output ps2_kbd_clk_out,
output ps2_kbd_data_out,
@ -106,7 +119,7 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0
);
@ -135,7 +148,7 @@ assign forced_scandoubler = cfg[4];
//cfg[5] - ypbpr handled in sys_top
// command byte read by the io controller
wire [15:0] sd_cmd =
wire [15:0] sd_cmd =
{
2'b00,
(VDNUM>=4) ? sd_wr[3] : 1'b0,
@ -145,7 +158,7 @@ wire [15:0] sd_cmd =
(VDNUM>=4) ? sd_rd[3] : 1'b0,
(VDNUM>=3) ? sd_rd[2] : 1'b0,
(VDNUM>=2) ? sd_rd[1] : 1'b0,
4'h5, sd_conf, 1'b1,
sd_wr[0],
sd_rd[0]
@ -261,13 +274,22 @@ always@(posedge clk_sys) begin
reg [2:0] b_wr;
reg [2:0] stick_idx;
reg ps2skip = 0;
reg [3:0] stflg = 0;
reg [31:0] status_req;
reg old_status_set = 0;
old_status_set <= status_set;
if(~old_status_set & status_set) begin
stflg <= stflg + 1'd1;
status_req <= status_in;
end
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
if(~io_enable) begin
if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5 && !ps2skip) begin
@ -297,6 +319,8 @@ always@(posedge clk_sys) begin
'h19: sd_ack_conf <= 1;
'h17,
'h18: sd_ack <= 1;
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= 1;
endcase
sd_buff_addr <= 0;
@ -306,11 +330,15 @@ always@(posedge clk_sys) begin
case(cmd)
// buttons and switches
'h01: cfg <= io_din[7:0];
'h01: cfg <= io_din[7:0];
'h02: joystick_0 <= io_din;
'h03: joystick_1 <= io_din;
'h10: joystick_2 <= io_din;
'h11: joystick_3 <= io_din;
'h12: joystick_4 <= io_din;
'h13: joystick_5 <= io_din;
// store incoming ps2 mouse bytes
// store incoming ps2 mouse bytes
'h04: begin
mouse_data <= io_din[7:0];
mouse_we <= 1;
@ -324,7 +352,7 @@ always@(posedge clk_sys) begin
end
end
// store incoming ps2 keyboard bytes
// store incoming ps2 keyboard bytes
'h05: begin
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
@ -332,20 +360,15 @@ always@(posedge clk_sys) begin
kbd_we <= 1;
end
// reading config string
'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
end
// reading config string, returning a byte from string
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
// reading sd card status
'h16: begin
case(byte_cnt)
'h16: case(byte_cnt)
1: io_dout <= sd_cmd;
2: io_dout <= sd_lba[15:0];
3: io_dout <= sd_lba[31:16];
endcase
end
// send SD config IO -> FPGA
// flag that download begins
@ -366,14 +389,17 @@ always@(posedge clk_sys) begin
end
// joystick analog
'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= io_din[2:0];
if(byte_cnt == 2) begin
if(stick_idx == 0) joystick_analog_0 <= io_din;
if(stick_idx == 1) joystick_analog_1 <= io_din;
end
end
'h1a: case(byte_cnt)
1: stick_idx <= io_din[2:0]; // first byte is joystick index
2: case(stick_idx)
0: joystick_analog_0 <= io_din;
1: joystick_analog_1 <= io_din;
2: joystick_analog_2 <= io_din;
3: joystick_analog_3 <= io_din;
4: joystick_analog_4 <= io_din;
5: joystick_analog_5 <= io_din;
endcase
endcase
// notify image selection
'h1c: begin
@ -392,41 +418,46 @@ always@(posedge clk_sys) begin
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
// reading ps2 keyboard/mouse control
'h21: begin
if(byte_cnt == 1) begin
'h21: if(byte_cnt == 1) begin
io_dout <= kbd_data_host;
kbd_rd <= 1;
end
else
if(byte_cnt == 2) begin
io_dout <= mouse_data_host;
mouse_rd <= 1;
end
end
//RTC
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//Video res.
'h23: begin
case(byte_cnt)
1: io_dout <= vid_nres;
2: io_dout <= vid_hcnt[15:0];
3: io_dout <= vid_hcnt[31:16];
4: io_dout <= vid_vcnt[15:0];
5: io_dout <= vid_vcnt[31:16];
6: io_dout <= vid_htime[15:0];
7: io_dout <= vid_htime[31:16];
8: io_dout <= vid_vtime[15:0];
9: io_dout <= vid_vtime[31:16];
10: io_dout <= vid_pix[15:0];
11: io_dout <= vid_pix[31:16];
12: io_dout <= vid_vtime_hdmi[15:0];
13: io_dout <= vid_vtime_hdmi[31:16];
endcase
end
'h23: case(byte_cnt)
1: io_dout <= vid_nres;
2: io_dout <= vid_hcnt[15:0];
3: io_dout <= vid_hcnt[31:16];
4: io_dout <= vid_vcnt[15:0];
5: io_dout <= vid_vcnt[31:16];
6: io_dout <= vid_htime[15:0];
7: io_dout <= vid_htime[31:16];
8: io_dout <= vid_vtime[15:0];
9: io_dout <= vid_vtime[31:16];
10: io_dout <= vid_pix[15:0];
11: io_dout <= vid_pix[31:16];
12: io_dout <= vid_vtime_hdmi[15:0];
13: io_dout <= vid_vtime_hdmi[31:16];
endcase
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//UART flags
'h28: io_dout <= uart_mode;
//status set
'h29: case(byte_cnt)
1: io_dout <= status_req[15:0];
2: io_dout <= status_req[31:16];
endcase
endcase
end
end
@ -460,7 +491,7 @@ ps2_device keyboard
.ps2_clk(clk_ps2),
.ps2_clk_out(ps2_kbd_clk_out),
.ps2_dat_out(ps2_kbd_data_out),
.ps2_clk_in(ps2_kbd_clk_in || !PS2WE),
.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
@ -538,7 +569,7 @@ always@(posedge clk_sys) begin
begin
if(io_din[7:0]) begin
addr <= 0;
ioctl_download <= 1;
ioctl_download <= 1;
end else begin
ioctl_addr <= addr;
ioctl_download <= 0;
@ -577,7 +608,7 @@ module ps2_device #(parameter PS2_FIFO_BITS=5)
input ps2_clk_in,
input ps2_dat_in,
output [8:0] rdata,
input rd
);
@ -632,7 +663,7 @@ always@(posedge clk_sys) begin
rx_state <= rx_state + 1'b1;
rx_cnt <= 0;
end
2: begin
if(rx_cnt <= 7) data <= {d1, data[7:1]};
else rx_state <= rx_state + 1'b1;
@ -643,7 +674,7 @@ always@(posedge clk_sys) begin
rx_state <= rx_state + 1'b1;
ps2_dat_out <= 0;
end
4: begin
ps2_dat_out <= 1;
has_data <= 1;
@ -678,7 +709,7 @@ always@(posedge clk_sys) begin
if((tx_state >= 1)&&(tx_state < 9)) begin
ps2_dat_out <= tx_byte[0]; // data bits
tx_byte[6:0] <= tx_byte[7:1]; // shift down
if(tx_byte[0])
if(tx_byte[0])
parity <= !parity;
end

190
sys/i2s.v
View File

@ -1,136 +1,54 @@
module i2s
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_DW = 16,
parameter AUDIO_RATE = 96000
)
(
input reset,
input clk_sys,
input half_rate,
output reg sclk,
output reg lrclk,
output reg sdata,
input [AUDIO_DW-1:0] left_chan,
input [AUDIO_DW-1:0] right_chan
);
localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
localparam ERROR_BASE = 10000;
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
reg lpf_ce;
wire [AUDIO_DW-1:0] al, ar;
lpf_i2s lpf_l
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(left_chan),
.ODATA(al)
);
lpf_i2s lpf_r
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(right_chan),
.ODATA(ar)
);
always @(posedge clk_sys) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg [7:0] bit_cnt;
reg skip = 0;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
reg msclk;
reg ce;
lpf_ce <= 0;
if (reset) begin
count_q <= 0;
error_q <= 0;
ce <= 0;
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
sclk <= msclk;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) begin
msclk <= ~msclk;
if(msclk) begin
skip <= ~skip;
if(skip) lpf_ce <= 1;
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= al;
right <= ar;
end
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
end
endmodule
module lpf_i2s
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule
module i2s
#(
parameter AUDIO_DW = 16
)
(
input reset,
input clk,
input ce,
output reg sclk,
output reg lrclk,
output reg sdata,
input [AUDIO_DW-1:0] left_chan,
input [AUDIO_DW-1:0] right_chan
);
always @(posedge clk) begin
reg [7:0] bit_cnt;
reg msclk;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
if (reset) begin
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else begin
sclk <= msclk;
if(ce) begin
msclk <= ~msclk;
if(msclk) begin
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= left_chan;
right <= right_chan;
end
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
endmodule

60
sys/ip/avalon_combiner.v
View File

@ -1,60 +0,0 @@
// avalon_combiner.v
`timescale 1 ps / 1 ps
module avalon_combiner
(
input wire clk, // clock.clk
input wire rst, // reset.reset
output wire [6:0] mixer_address, // ctl_mixer.address
output wire [3:0] mixer_byteenable, // .byteenable
output wire mixer_write, // .write
output wire [31:0] mixer_writedata, // .writedata
input wire mixer_waitrequest, // .waitrequest
output wire [6:0] scaler_address, // ctl_scaler.address
output wire [3:0] scaler_byteenable, // .byteenable
input wire scaler_waitrequest, // .waitrequest
output wire scaler_write, // .write
output wire [31:0] scaler_writedata, // .writedata
output wire [7:0] video_address, // ctl_video.address
output wire [3:0] video_byteenable, // .byteenable
input wire video_waitrequest, // .waitrequest
output wire video_write, // .write
output wire [31:0] video_writedata, // .writedata
output wire clock, // control.clock
output wire reset, // .reset
input wire [8:0] address, // .address
input wire write, // .write
input wire [31:0] writedata, // .writedata
output wire waitrequest // .waitrequest
);
assign clock = clk;
assign reset = rst;
assign mixer_address = address[6:0];
assign scaler_address = address[6:0];
assign video_address = address[7:0];
assign mixer_byteenable = 4'b1111;
assign scaler_byteenable = 4'b1111;
assign video_byteenable = 4'b1111;
wire en_scaler = (address[8:7] == 0);
wire en_mixer = (address[8:7] == 1);
wire en_video = address[8];
assign mixer_write = en_mixer & write;
assign scaler_write = en_scaler & write;
assign video_write = en_video & write;
assign mixer_writedata = writedata;
assign scaler_writedata = writedata;
assign video_writedata = writedata;
assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
endmodule

204
sys/ip/avalon_combiner_hw.tcl
View File

@ -1,204 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Wed Dec 13 01:40:49 CST 2017
# DO NOT MODIFY
#
# avalon_combiner "avalon_combiner" v17.0
# sorgelig 2017.12.13.01:40:49
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module avalon_combiner
#
set_module_property DESCRIPTION ""
set_module_property NAME avalon_combiner
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR sorgelig
set_module_property DISPLAY_NAME avalon_combiner
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset rst reset Input 1
#
# connection point ctl_mixer
#
add_interface ctl_mixer avalon start
set_interface_property ctl_mixer addressUnits WORDS
set_interface_property ctl_mixer associatedClock clock
set_interface_property ctl_mixer associatedReset reset
set_interface_property ctl_mixer bitsPerSymbol 8
set_interface_property ctl_mixer burstOnBurstBoundariesOnly false
set_interface_property ctl_mixer burstcountUnits WORDS
set_interface_property ctl_mixer doStreamReads false
set_interface_property ctl_mixer doStreamWrites false
set_interface_property ctl_mixer holdTime 0
set_interface_property ctl_mixer linewrapBursts false
set_interface_property ctl_mixer maximumPendingReadTransactions 0
set_interface_property ctl_mixer maximumPendingWriteTransactions 0
set_interface_property ctl_mixer readLatency 0
set_interface_property ctl_mixer readWaitTime 1
set_interface_property ctl_mixer setupTime 0
set_interface_property ctl_mixer timingUnits Cycles
set_interface_property ctl_mixer writeWaitTime 0
set_interface_property ctl_mixer ENABLED true
set_interface_property ctl_mixer EXPORT_OF ""
set_interface_property ctl_mixer PORT_NAME_MAP ""
set_interface_property ctl_mixer CMSIS_SVD_VARIABLES ""
set_interface_property ctl_mixer SVD_ADDRESS_GROUP ""
add_interface_port ctl_mixer mixer_address address Output 7
add_interface_port ctl_mixer mixer_byteenable byteenable Output 4
add_interface_port ctl_mixer mixer_write write Output 1
add_interface_port ctl_mixer mixer_writedata writedata Output 32
add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1
#
# connection point ctl_scaler
#
add_interface ctl_scaler avalon start
set_interface_property ctl_scaler addressUnits WORDS
set_interface_property ctl_scaler associatedClock clock
set_interface_property ctl_scaler associatedReset reset
set_interface_property ctl_scaler bitsPerSymbol 8
set_interface_property ctl_scaler burstOnBurstBoundariesOnly false
set_interface_property ctl_scaler burstcountUnits WORDS
set_interface_property ctl_scaler doStreamReads false
set_interface_property ctl_scaler doStreamWrites false
set_interface_property ctl_scaler holdTime 0
set_interface_property ctl_scaler linewrapBursts false
set_interface_property ctl_scaler maximumPendingReadTransactions 0
set_interface_property ctl_scaler maximumPendingWriteTransactions 0
set_interface_property ctl_scaler readLatency 0
set_interface_property ctl_scaler readWaitTime 1
set_interface_property ctl_scaler setupTime 0
set_interface_property ctl_scaler timingUnits Cycles
set_interface_property ctl_scaler writeWaitTime 0
set_interface_property ctl_scaler ENABLED true
set_interface_property ctl_scaler EXPORT_OF ""
set_interface_property ctl_scaler PORT_NAME_MAP ""
set_interface_property ctl_scaler CMSIS_SVD_VARIABLES ""
set_interface_property ctl_scaler SVD_ADDRESS_GROUP ""
add_interface_port ctl_scaler scaler_address address Output 7
add_interface_port ctl_scaler scaler_byteenable byteenable Output 4
add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1
add_interface_port ctl_scaler scaler_write write Output 1
add_interface_port ctl_scaler scaler_writedata writedata Output 32
#
# connection point ctl_video
#
add_interface ctl_video avalon start
set_interface_property ctl_video addressUnits WORDS
set_interface_property ctl_video associatedClock clock
set_interface_property ctl_video associatedReset reset
set_interface_property ctl_video bitsPerSymbol 8
set_interface_property ctl_video burstOnBurstBoundariesOnly false
set_interface_property ctl_video burstcountUnits WORDS
set_interface_property ctl_video doStreamReads false
set_interface_property ctl_video doStreamWrites false
set_interface_property ctl_video holdTime 0
set_interface_property ctl_video linewrapBursts false
set_interface_property ctl_video maximumPendingReadTransactions 0
set_interface_property ctl_video maximumPendingWriteTransactions 0
set_interface_property ctl_video readLatency 0
set_interface_property ctl_video readWaitTime 1
set_interface_property ctl_video setupTime 0
set_interface_property ctl_video timingUnits Cycles
set_interface_property ctl_video writeWaitTime 0
set_interface_property ctl_video ENABLED true
set_interface_property ctl_video EXPORT_OF ""
set_interface_property ctl_video PORT_NAME_MAP ""
set_interface_property ctl_video CMSIS_SVD_VARIABLES ""
set_interface_property ctl_video SVD_ADDRESS_GROUP ""
add_interface_port ctl_video video_address address Output 8
add_interface_port ctl_video video_byteenable byteenable Output 4
add_interface_port ctl_video video_waitrequest waitrequest Input 1
add_interface_port ctl_video video_write write Output 1
add_interface_port ctl_video video_writedata writedata Output 32
#
# connection point control
#
add_interface control conduit end
set_interface_property control associatedClock clock
set_interface_property control associatedReset reset
set_interface_property control ENABLED true
set_interface_property control EXPORT_OF ""
set_interface_property control PORT_NAME_MAP ""
set_interface_property control CMSIS_SVD_VARIABLES ""
set_interface_property control SVD_ADDRESS_GROUP ""
add_interface_port control address address Input 9
add_interface_port control write write Input 1
add_interface_port control writedata writedata Input 32
add_interface_port control waitrequest waitrequest Output 1
add_interface_port control clock clock Output 1
add_interface_port control reset reset Output 1

3706
sys/ip/de10_hps_hw.tcl
View File

File diff suppressed because it is too large Load Diff

52
sys/ip/in_split.v
View File

@ -1,52 +0,0 @@
// in_split.v
`timescale 1 ps / 1 ps
module in_split (
input wire clk, // input.clk
input wire ce, // .ce
input wire de, // .de
input wire h_sync, // .h_sync
input wire v_sync, // .v_sync
input wire f, // .f
input wire [23:0] data, // .data
output wire vid_clk, // Output.vid_clk
output reg vid_datavalid, // .vid_datavalid
output reg [1:0] vid_de, // .vid_de
output reg [1:0] vid_f, // .vid_f
output reg [1:0] vid_h_sync, // .vid_h_sync
output reg [1:0] vid_v_sync, // .vid_v_sync
output reg [47:0] vid_data, // .vid_data
output wire vid_locked, // .vid_locked
output wire [7:0] vid_color_encoding, // .vid_color_encoding
output wire [7:0] vid_bit_width, // .vid_bit_width
input wire clipping, // .clipping
input wire overflow, // .overflow
input wire sof, // .sof
input wire sof_locked, // .sof_locked
input wire refclk_div, // .refclk_div
input wire padding // .padding
);
assign vid_bit_width = 0;
assign vid_color_encoding = 0;
assign vid_locked = 1;
assign vid_clk = clk;
always @(posedge clk) begin
reg odd = 0;
vid_datavalid <= 0;
if(ce) begin
vid_de[odd] <= de;
vid_f[odd] <= f;
vid_h_sync[odd] <= h_sync;
vid_v_sync[odd] <= v_sync;
if(odd) vid_data[47:24] <= data;
else vid_data[23:0] <= data;
odd <= ~odd;
vid_datavalid <= odd;
end
end
endmodule

104
sys/ip/in_split_hw.tcl
View File

@ -1,104 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 18:50:29 CST 2018
# DO NOT MODIFY
#
# in_split "Input Splitter" v17.0
# Sorgelig 2018.01.25.18:50:29
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module in_split
#
set_module_property DESCRIPTION ""
set_module_property NAME in_split
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Input Splitter"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input clk clk Input 1
add_interface_port input ce ce Input 1
add_interface_port input de de Input 1
add_interface_port input h_sync h_sync Input 1
add_interface_port input v_sync v_sync Input 1
add_interface_port input f f Input 1
add_interface_port input data data Input 24
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output vid_clk vid_clk Output 1
add_interface_port Output vid_datavalid vid_datavalid Output 1
add_interface_port Output vid_de vid_de Output 2
add_interface_port Output vid_f vid_f Output 2
add_interface_port Output vid_h_sync vid_h_sync Output 2
add_interface_port Output vid_v_sync vid_v_sync Output 2
add_interface_port Output vid_data vid_data Output 48
add_interface_port Output vid_locked vid_locked Output 1
add_interface_port Output vid_color_encoding vid_color_encoding Output 8
add_interface_port Output vid_bit_width vid_bit_width Output 8
add_interface_port Output clipping clipping Input 1
add_interface_port Output overflow overflow Input 1
add_interface_port Output sof sof Input 1
add_interface_port Output sof_locked sof_locked Input 1
add_interface_port Output refclk_div refclk_div Input 1
add_interface_port Output padding padding Input 1

44
sys/ip/out_mix.v
View File

@ -1,44 +0,0 @@
// out_mix.v
`timescale 1 ps / 1 ps
module out_mix (
input wire clk, // Output.clk
output reg de, // .de
output reg h_sync, // .h_sync
output reg v_sync, // .v_sync
output reg [23:0] data, // .data
output reg vid_clk, // input.vid_clk
input wire [1:0] vid_datavalid, // .vid_datavalid
input wire [1:0] vid_h_sync, // .vid_h_sync
input wire [1:0] vid_v_sync, // .vid_v_sync
input wire [47:0] vid_data, // .vid_data
input wire underflow, // .underflow
input wire vid_mode_change, // .vid_mode_change
input wire [1:0] vid_std, // .vid_std
input wire [1:0] vid_f, // .vid_f
input wire [1:0] vid_h, // .vid_h
input wire [1:0] vid_v // .vid_v
);
reg r_de;
reg r_h_sync;
reg r_v_sync;
reg [23:0] r_data;
always @(posedge clk) begin
vid_clk <= ~vid_clk;
if(~vid_clk) begin
{r_de,de} <= vid_datavalid;
{r_h_sync, h_sync} <= vid_h_sync;
{r_v_sync, v_sync} <= vid_v_sync;
{r_data, data} <= vid_data;
end else begin
de <= r_de;
h_sync <= r_h_sync;
v_sync <= r_v_sync;
data <= r_data;
end
end
endmodule

97
sys/ip/out_mix_hw.tcl
View File

@ -1,97 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 06:51:26 CST 2018
# DO NOT MODIFY
#
# out_mix "Output Mixer" v1.0
# Sorgelig 2018.01.25.06:51:26
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module out_mix
#
set_module_property DESCRIPTION ""
set_module_property NAME out_mix
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Output Mixer"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output clk clk Input 1
add_interface_port Output de de Output 1
add_interface_port Output h_sync h_sync Output 1
add_interface_port Output v_sync v_sync Output 1
add_interface_port Output data data Output 24
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input vid_clk vid_clk Output 1
add_interface_port input vid_datavalid vid_datavalid Input 2
add_interface_port input vid_h_sync vid_h_sync Input 2
add_interface_port input vid_v_sync vid_v_sync Input 2
add_interface_port input vid_data vid_data Input 48
add_interface_port input underflow underflow Input 1
add_interface_port input vid_mode_change vid_mode_change Input 1
add_interface_port input vid_std vid_std Input 2
add_interface_port input vid_f vid_f Input 2
add_interface_port input vid_h vid_h Input 2
add_interface_port input vid_v vid_v Input 2

50
sys/ip/reset_source.v
View File

@ -1,50 +0,0 @@
// reset_source.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module reset_source
(
input wire clk, // clock.clk
input wire reset_hps, // reset_hps.reset
output wire reset_sys, // reset_sys.reset
output wire reset_cold, // reset_cold.reset
input wire cold_req, // reset_ctl.cold_req
output wire reset, // .reset
input wire reset_req, // .reset_req
input wire reset_vip, // .reset_vip
input wire warm_req, // .warm_req
output wire reset_warm // reset_warm.reset
);
assign reset_cold = cold_req;
assign reset_warm = warm_req;
wire reset_m = sys_reset | reset_hps | reset_req;
assign reset = reset_m;
assign reset_sys = reset_m | reset_vip;
reg sys_reset = 1;
always @(posedge clk) begin
integer timeout = 0;
reg reset_lock = 0;
reset_lock <= reset_lock | cold_req;
if(timeout < 2000000) begin
sys_reset <= 1;
timeout <= timeout + 1;
reset_lock <= 0;
end
else begin
sys_reset <= reset_lock;
end
end
endmodule

152
sys/ip/reset_source_hw.tcl
View File

@ -1,152 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Tue Feb 20 07:55:55 CST 2018
# DO NOT MODIFY
#
# reset_source "reset_source" v17.0
# Sorgelig 2018.02.20.07:55:55
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module reset_source
#
set_module_property DESCRIPTION ""
set_module_property NAME reset_source
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME reset_source
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset_hps
#
add_interface reset_hps reset end
set_interface_property reset_hps associatedClock ""
set_interface_property reset_hps synchronousEdges NONE
set_interface_property reset_hps ENABLED true
set_interface_property reset_hps EXPORT_OF ""
set_interface_property reset_hps PORT_NAME_MAP ""
set_interface_property reset_hps CMSIS_SVD_VARIABLES ""
set_interface_property reset_hps SVD_ADDRESS_GROUP ""
add_interface_port reset_hps reset_hps reset Input 1
#
# connection point reset_sys
#
add_interface reset_sys reset start
set_interface_property reset_sys associatedClock ""
set_interface_property reset_sys associatedDirectReset ""
set_interface_property reset_sys associatedResetSinks ""
set_interface_property reset_sys synchronousEdges NONE
set_interface_property reset_sys ENABLED true
set_interface_property reset_sys EXPORT_OF ""
set_interface_property reset_sys PORT_NAME_MAP ""
set_interface_property reset_sys CMSIS_SVD_VARIABLES ""
set_interface_property reset_sys SVD_ADDRESS_GROUP ""
add_interface_port reset_sys reset_sys reset Output 1
#
# connection point reset_ctl
#
add_interface reset_ctl conduit end
set_interface_property reset_ctl associatedClock ""
set_interface_property reset_ctl associatedReset ""
set_interface_property reset_ctl ENABLED true
set_interface_property reset_ctl EXPORT_OF ""
set_interface_property reset_ctl PORT_NAME_MAP ""
set_interface_property reset_ctl CMSIS_SVD_VARIABLES ""
set_interface_property reset_ctl SVD_ADDRESS_GROUP ""
add_interface_port reset_ctl cold_req cold_req Input 1
add_interface_port reset_ctl reset reset Output 1
add_interface_port reset_ctl reset_req reset_req Input 1
add_interface_port reset_ctl warm_req warm_req Input 1
add_interface_port reset_ctl reset_vip reset_vip Input 1
#
# connection point reset_warm
#
add_interface reset_warm reset start
set_interface_property reset_warm associatedClock ""
set_interface_property reset_warm associatedDirectReset ""
set_interface_property reset_warm associatedResetSinks ""
set_interface_property reset_warm synchronousEdges NONE
set_interface_property reset_warm ENABLED true
set_interface_property reset_warm EXPORT_OF ""
set_interface_property reset_warm PORT_NAME_MAP ""
set_interface_property reset_warm CMSIS_SVD_VARIABLES ""
set_interface_property reset_warm SVD_ADDRESS_GROUP ""
add_interface_port reset_warm reset_warm reset Output 1
#
# connection point reset_cold
#
add_interface reset_cold reset start
set_interface_property reset_cold associatedClock ""
set_interface_property reset_cold associatedDirectReset ""
set_interface_property reset_cold associatedResetSinks ""
set_interface_property reset_cold synchronousEdges NONE
set_interface_property reset_cold ENABLED true
set_interface_property reset_cold EXPORT_OF ""
set_interface_property reset_cold PORT_NAME_MAP ""
set_interface_property reset_cold CMSIS_SVD_VARIABLES ""
set_interface_property reset_cold SVD_ADDRESS_GROUP ""
add_interface_port reset_cold reset_cold reset Output 1

100
sys/lpf48k.sv
View File

@ -1,100 +0,0 @@
// low pass filter
// Revision 1.00
//
// Copyright (c) 2008 Takayuki Hara.
// All rights reserved.
//
// Redistribution and use of this source code or any derivative works, are
// permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// 3. Redistributions may not be sold, nor may they be used in a commercial
// product or activity without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// LPF (cut off 48kHz at 3.58MHz)
module lpf48k #(parameter MSB = 15)
(
input RESET,
input CLK,
input CE,
input ENABLE,
input [MSB:0] IDATA,
output [MSB:0] ODATA
);
wire [7:0] LPF_TAP_DATA[0:71] =
'{
8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09,
8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B,
8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D,
8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D,
8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B,
8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09,
8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51
};
reg [7:0] FF_ADDR = 0;
reg [MSB+10:0] FF_INTEG = 0;
wire [MSB+8:0] W_DATA;
wire W_ADDR_END;
assign W_ADDR_END = ((FF_ADDR == 71));
reg [MSB:0] OUT;
assign ODATA = ENABLE ? OUT : IDATA;
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_ADDR <= 0;
else
begin
if (CE) begin
if (W_ADDR_END) FF_ADDR <= 0;
else FF_ADDR <= FF_ADDR + 1'd1;
end
end
end
assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA;
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_INTEG <= 0;
else
begin
if (CE) begin
if (W_ADDR_END) FF_INTEG <= 0;
else FF_INTEG <= FF_INTEG + W_DATA;
end
end
end
always @(posedge RESET or posedge CLK) begin
if (RESET) OUT <= 0;
else
begin
if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10];
end
end
endmodule

130
sys/osd.v
View File

@ -13,7 +13,8 @@ module osd
input [23:0] din,
output [23:0] dout,
input de_in,
output reg de_out
output reg de_out,
output reg osd_status
);
parameter OSD_COLOR = 3'd4;
@ -23,21 +24,24 @@ parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64;
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096];
reg osd_enable;
reg [7:0] osd_buffer[4096];
reg highres = 0;
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infoy;
reg [21:0] hrheight;
always@(posedge clk_sys) begin
reg [11:0] bcnt;
reg [7:0] cmd;
reg has_cmd;
reg old_strobe;
reg highres = 0;
hrheight <= info ? infoh : (OSD_HEIGHT<<highres);
old_strobe <= io_strobe;
@ -53,9 +57,9 @@ always@(posedge clk_sys) begin
cmd <= io_din[7:0];
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(io_din[7:4] == 4) begin
if(!io_din[0]) highres <= 0;
info <= io_din[2];
bcnt <= 0;
if(!io_din[0]) {osd_status,highres} <= 0;
else {osd_status,info} <= {~io_din[2],io_din[2]};
bcnt <= 0;
end
// command 0x20: OSDCMDWRITE
if(io_din[7:4] == 2) begin
@ -101,98 +105,90 @@ always @(negedge clk_video) begin
end
end
reg [23:0] h_cnt;
reg [21:0] v_cnt;
reg [21:0] dsp_width;
reg [21:0] dsp_height;
reg [7:0] osd_byte;
reg [21:0] osd_vcnt;
reg [21:0] fheight;
reg [21:0] finfoy;
wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT<<highres);
reg [2:0] osd_de;
reg osd_pixel;
always @(posedge clk_video) begin
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg [7:0] osd_byte;
reg [23:0] h_cnt;
reg [21:0] v_cnt;
reg [21:0] dsp_width;
reg [21:0] osd_vcnt;
reg [21:0] h_osd_start;
reg [21:0] v_osd_start;
reg [21:0] osd_hcnt;
reg osd_de1,osd_de2;
reg [1:0] osd_en;
if(ce_pix) begin
deD <= de_in;
if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
if (h_cnt == h_osd_start) begin
osd_de[0] <= osd_en[1] && hrheight && (osd_vcnt < hrheight);
osd_hcnt <= 0;
end
if (osd_hcnt+1 == (info ? infow : OSD_WIDTH)) osd_de[0] <= 0;
// falling edge of de
if(!de_in && deD) dsp_width <= h_cnt[21:0];
// rising edge of de
if(de_in && !deD) begin
h_cnt <= 0;
v_cnt <= v_cnt + 1'd1;
h_osd_start <= info ? infox : (((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET - 2'd2);
if(h_cnt > {dsp_width, 2'b00}) begin
v_cnt <= 0;
dsp_height <= v_cnt;
if(osd_enable) begin
if(v_cnt<320) begin
multiscan <= 0;
fheight <= hrheight;
finfoy <= infoy;
end
else if(v_cnt<640) begin
multiscan <= 1;
fheight <= hrheight << 1;
finfoy <= infoy << 1;
end
else if(v_cnt<960) begin
multiscan <= 2;
fheight <= hrheight + (hrheight<<1);
finfoy <= infoy + (infoy << 1);
end
else begin
multiscan <= 3;
fheight <= hrheight << 2;
finfoy <= infoy << 2;
end
osd_en <= (osd_en << 1) | osd_enable;
if(~osd_enable) osd_en <= 0;
if(v_cnt<320) begin
multiscan <= 0;
v_osd_start <= info ? infoy : (((v_cnt-hrheight)>>1) + OSD_Y_OFFSET);
end
else if(v_cnt<640) begin
multiscan <= 1;
v_osd_start <= info ? (infoy<<1) : (((v_cnt-(hrheight<<1))>>1) + OSD_Y_OFFSET);
end
else if(v_cnt<960) begin
multiscan <= 2;
v_osd_start <= info ? (infoy + (infoy << 1)) : (((v_cnt-(hrheight + (hrheight<<1)))>>1) + OSD_Y_OFFSET);
end
else begin
fheight <= 0;
multiscan <= 3;
v_osd_start <= info ? (infoy<<2) : (((v_cnt-(hrheight<<2))>>1) + OSD_Y_OFFSET);
end
end
h_cnt <= 0;
osd_div <= osd_div + 1'd1;
if(osd_div == multiscan) begin
osd_div <= 0;
osd_vcnt <= osd_vcnt + 1'd1;
if(~&osd_vcnt) osd_vcnt <= osd_vcnt + 1'd1;
end
if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
end
osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
osd_pixel <= osd_byte[osd_vcnt[2:0]];
osd_de[2:1] <= osd_de[1:0];
end
end
// area in which OSD is being displayed
wire [21:0] h_osd_start = info ? infox : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
wire [21:0] h_osd_end = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH);
wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
wire [21:0] v_osd_end = v_osd_start + fheight;
wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1;
wire osd_de = osd_enable && fheight &&
(h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
wire osd_pixel = osd_byte[osd_vcnt[2:0]];
reg [23:0] rdout;
assign dout = rdout;
always @(posedge clk_video) begin
rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
rdout <= ~osd_de[2] ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
de_out <= de_in;
end

120
sys/pattern_vg.v
View File

@ -1,120 +0,0 @@
module pattern_vg
#(
parameter B=8, // number of bits per channel
X_BITS=13,
Y_BITS=13,
FRACTIONAL_BITS = 12
)
(
input reset, clk_in,
input wire [X_BITS-1:0] x,
input wire [Y_BITS-1:0] y,
input wire vn_in, hn_in, dn_in,
input wire [B-1:0] r_in, g_in, b_in,
output reg vn_out, hn_out, den_out,
output reg [B-1:0] r_out, g_out, b_out,
input wire [X_BITS-1:0] total_active_pix,
input wire [Y_BITS-1:0] total_active_lines,
input wire [7:0] pattern,
input wire [B+FRACTIONAL_BITS-1:0] ramp_step
);
reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values
//wire bar_0 = y<90;
wire bar_1 = y>=90 & y<180;
wire bar_2 = y>=180 & y<270;
wire bar_3 = y>=270 & y<360;
wire bar_4 = y>=360 & y<450;
wire bar_5 = y>=450 & y<540;
wire bar_6 = y>=540 & y<630;
wire bar_7 = y>=630 & y<720;
wire red_enable = bar_1 | bar_3 | bar_5 | bar_7;
wire green_enable = bar_2 | bar_3 | bar_6 | bar_7;
wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7;
always @(posedge clk_in)
begin
vn_out <= vn_in;
hn_out <= hn_in;
den_out <= dn_in;
if (reset)
ramp_values <= 0;
else if (pattern == 8'b0) // no pattern
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
else if (pattern == 8'b1) // border
begin
if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else // Double-border (OzOnE)...
if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
begin
r_out <= 8'hD0;
g_out <= 8'hB0;
b_out <= 8'hB0;
end
else
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
end
else if (pattern == 8'd2) // moireX
begin
if ((dn_in) && x[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd3) // moireY
begin
if ((dn_in) && y[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd4) // Simple RAMP
begin
r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
if ((x == total_active_pix - 1) && (dn_in))
ramp_values <= 0;
else if ((x == 0) && (dn_in))
ramp_values <= ramp_step;
else if (dn_in)
ramp_values <= ramp_values + ramp_step;
end
end
endmodule

4
sys/pll_hdmi/pll_hdmi_0002_q13.qip Normal file
View File

@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

360
sys/pll_hdmi_adj.vhd Normal file
View File

@ -0,0 +1,360 @@
--------------------------------------------------------------------------------
-- HDMI PLL Adjust
--------------------------------------------------------------------------------
-- Changes the HDMI PLL frequency according to the scaler suggestions.
--------------------------------------------
-- LLTUNE :
-- 0 : Input Syncline
-- 1 :
-- 2 : Input Interlaced mode
-- 3 : Input Interlaced field
-- 4 : Output Syncline
-- 5 :
-- 6 : Input clock
-- 7 : Output clock
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY pll_hdmi_adj IS
PORT (
-- Scaler
llena : IN std_logic; -- 0=Disabled 1=Enabled
lltune : IN unsigned(15 DOWNTO 0); -- Outputs from scaler
locked : OUT std_logic;
-- Signals from reconfig commands
i_waitrequest : OUT std_logic;
i_write : IN std_logic;
i_address : IN unsigned(5 DOWNTO 0);
i_writedata : IN unsigned(31 DOWNTO 0);
-- Outputs to PLL_HDMI_CFG
o_waitrequest : IN std_logic;
o_write : OUT std_logic;
o_address : OUT unsigned(5 DOWNTO 0);
o_writedata : OUT unsigned(31 DOWNTO 0);
------------------------------------
clk : IN std_logic;
reset_na : IN std_logic
);
BEGIN
END ENTITY pll_hdmi_adj;
--##############################################################################
ARCHITECTURE rtl OF pll_hdmi_adj IS
SIGNAL pwrite : std_logic;
SIGNAL paddress : unsigned(5 DOWNTO 0);
SIGNAL pdata : unsigned(31 DOWNTO 0);
TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6);
SIGNAL state : enum_state;
SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0);
SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0);
SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0);
SIGNAL mul : unsigned(15 DOWNTO 0);
SIGNAL sign,sign_pre : std_logic;
SIGNAL up,modo,phm,dir : std_logic;
SIGNAL cpt : natural RANGE 0 TO 3;
SIGNAL col : natural RANGE 0 TO 15;
SIGNAL icpt,ocpt,ssh : natural RANGE 0 TO 2**24-1;
SIGNAL isync,isync2,itog,ipulse : std_logic;
SIGNAL osync,osync2,otog,opulse : std_logic;
SIGNAL sync,pulse,los,lop : std_logic;
SIGNAL osize,isize,offset,osizep : signed(23 DOWNTO 0);
SIGNAL logcpt : natural RANGE 0 TO 31;
SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0;
BEGIN
----------------------------------------------------------------------------
-- Sample image sizes
Sampler:PROCESS(clk,reset_na) IS
BEGIN
IF reset_na='0' THEN
--pragma synthesis_off
otog<='0';
itog<='0';
isync<='0';
isync2<='0';
osync<='0';
osync2<='0';
--pragma synthesis_on
ELSIF rising_edge(clk) THEN
-- Clock domain crossing
isync<=lltune(0); -- <ASYNC>
isync2<=isync;
osync<=lltune(4); -- <ASYNC>
osync2<=osync;
itog<=itog XOR (isync AND NOT isync2);
otog<=otog XOR (osync AND NOT osync2);
--ipulse<=isync AND NOT isync2 AND itog;
--opulse<=osync AND NOT osync2 AND otog;
-- Measure output image size
IF osync='1' AND osync2='0' AND otog='1' THEN
ocpt<=0;
osizep<=to_signed(ocpt,24);
ELSE
ocpt<=ocpt+1;
END IF;
-- Measure input image size
IF isync='1' AND isync2='0' AND itog='1' THEN
icpt<=0;
--isize<=to_signed(icpt,24);
osize<=osizep;
offset<=to_signed(ocpt,24);
udiff<=integer(to_integer(osizep)) - integer(icpt);
sync<='1';
ELSE
icpt<=icpt+1;
sync<='0';
END IF;
--------------------------------------------
pulse<='0';
IF sync='1' THEN
logcpt<=0;
ssh<=to_integer(osize);
los<='0';
lop<='0';
ELSIF logcpt<24 THEN
-- Frequency difference
IF udiff>0 AND ssh<udiff AND los='0' THEN
tune_freq<='0' & to_unsigned(logcpt,5);
los<='1';
ELSIF udiff<=0 AND ssh<-udiff AND los='0' THEN
tune_freq<='1' & to_unsigned(logcpt,5);
los<='1';
END IF;
-- Phase difference
IF offset<osize/2 AND ssh<offset AND lop='0' THEN
tune_phase<='0' & to_unsigned(logcpt,5);
lop<='1';
ELSIF offset>=osize/2 AND ssh<(osize-offset) AND lop='0' THEN
tune_phase<='1' & to_unsigned(logcpt,5);
lop<='1';
END IF;
ssh<=ssh/2;
logcpt<=logcpt+1;
ELSIF logcpt=24 THEN
pulse<='1';
ssh<=ssh/2;
logcpt<=logcpt+1;
END IF;
END IF;
END PROCESS Sampler;
----------------------------------------------------------------------------
-- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf.
-- 000100 : M counter
-- 000111 : M counter Fractional Value K
Comb:PROCESS(i_write,i_address,
i_writedata,pwrite,paddress,pdata) IS
BEGIN
IF i_write='1' THEN
o_write <=i_write;
o_address <=i_address;
o_writedata <=i_writedata;
ELSE
o_write <=pwrite;
o_address <=paddress;
o_writedata<=pdata;
END IF;
END PROCESS Comb;
i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0';
----------------------------------------------------------------------------
Schmurtz:PROCESS(clk,reset_na) IS
VARIABLE off_v,ofp_v : natural RANGE 0 TO 63;
VARIABLE diff_v : unsigned(40 DOWNTO 0);
VARIABLE mulco : unsigned(15 DOWNTO 0);
VARIABLE up_v,sign_v : std_logic;
BEGIN
IF reset_na='0' THEN
modo<='0';
state<=sIDLE;
ELSIF rising_edge(clk) THEN
------------------------------------------------------
-- Snoop accesses to PLL reconfiguration
IF i_address="000100" AND i_write='1' THEN
mfrac (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mul<=i_writedata(15 DOWNTO 0);
modo<='1';
END IF;
IF i_address="000111" AND i_write='1' THEN
mfrac (31 DOWNTO 0)<=i_writedata;
mfrac_ref(31 DOWNTO 0)<=i_writedata;
mfrac_mem(31 DOWNTO 0)<=i_writedata;
modo<='1';
END IF;
------------------------------------------------------
-- Tuning
off_v:=to_integer('0' & tune_freq(4 DOWNTO 0));
ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0));
--IF off_v<8 THEN off_v:=8; END IF;
--IF ofp_v<7 THEN ofp_v:=7; END IF;
IF off_v<4 THEN off_v:=4; END IF;
IF ofp_v<4 THEN ofp_v:=4; END IF;
IF off_v>=18 AND ofp_v>=18 THEN
locked<=llena;
ELSE
locked<='0';
END IF;
up_v:='0';
IF pulse='1' THEN
cpt<=(cpt+1) MOD 4;
IF llena='0' THEN
-- Recover original freq when disabling low lag mode
cpt<=0;
col<=0;
IF modo='1' THEN
mfrac<=mfrac_mem;
mfrac_ref<=mfrac_mem;
up<='1';
modo<='0';
END IF;
ELSIF phm='0' AND cpt=0 THEN
-- Frequency adjust
sign_v:=tune_freq(5);
IF col<10 THEN col<=col+1; END IF;
IF off_v>=16 AND col>=10 THEN
phm<='1';
col<=0;
ELSE
off_v:=off_v+1;
IF off_v>17 THEN
off_v:=off_v + 3;
END IF;
up_v:='1';
up<='1';
END IF;
ELSIF cpt=0 THEN
-- Phase adjust
sign_v:=NOT tune_phase(5);
col<=col+1;
IF col>=10 THEN
phm<='0';
up_v:='1';
off_v:=31;
col<=0;
ELSE
off_v:=ofp_v + 1;
IF ofp_v>7 THEN
off_v:=off_v + 1;
END IF;
IF ofp_v>14 THEN
off_v:=off_v + 2;
END IF;
IF ofp_v>17 THEN
off_v:=off_v + 3;
END IF;
up_v:='1';
END IF;
up<='1';
END IF;
END IF;
diff_v:=shift_right(mfrac_ref,off_v);
IF sign_v='0' THEN
diff_v:=mfrac_ref + diff_v;
ELSE
diff_v:=mfrac_ref - diff_v;
END IF;
IF up_v='1' THEN
mfrac<=diff_v;
END IF;
IF up_v='1' AND phm='0' THEN
mfrac_ref<=diff_v;
END IF;
------------------------------------------------------
-- Update PLL registers
mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32)));
CASE state IS
WHEN sIDLE =>
pwrite<='0';
IF up='1' THEN
up<='0';
IF mulco/=mul THEN
state<=sW1;
ELSE
state<=sW3;
END IF;
END IF;
WHEN sW1 => -- Change M multiplier
mul<=mulco;
pdata<=x"0000" & mulco;
paddress<="000100";
pwrite<='1';
state<=sW2;
WHEN sW2 =>
IF pwrite='1' AND o_waitrequest='0' THEN
state<=sW3;
pwrite<='0';
END IF;
WHEN sW3 => -- Change M fractional value
pdata<=mfrac(31 DOWNTO 0);
paddress<="000111";
pwrite<='1';
state<=sW4;
WHEN sW4 =>
IF pwrite='1' AND o_waitrequest='0' THEN
state<=sW5;
pwrite<='0';
END IF;
WHEN sW5 =>
pdata<=x"0000_0001";
paddress<="000010";
pwrite<='1';
state<=sW6;
WHEN sW6 =>
IF pwrite='1' AND o_waitrequest='0' THEN
pwrite<='0';
state<=sIDLE;
END IF;
END CASE;
END IF;
END PROCESS Schmurtz;
----------------------------------------------------------------------------
END ARCHITECTURE rtl;

13
sys/pll_hdmi_q13.qip Normal file
View File

@ -0,0 +1,13 @@
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"

168
sys/scandoubler.v
View File

@ -2,7 +2,7 @@
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
// Copyright (c) 2017-2019 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
@ -31,8 +31,8 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
// shifter video interface
input hs_in,
input vs_in,
input hb_in,
input vb_in,
input hb_in,
input vb_in,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
@ -42,8 +42,8 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
// output interface
output reg hs_out,
output vs_out,
output hb_out,
output vb_out,
output hb_out,
output vb_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
@ -56,42 +56,51 @@ assign vs_out = vso[3];
assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
//Compensate picture shift after HQ2x
assign vb_out = vbo[2];
assign vb_out = vbo[3];
assign hb_out = hbo[6];
reg [7:0] pix_len = 0;
reg [7:0] pix_cnt = 0;
wire [7:0] pl = pix_len + 1'b1;
wire [7:0] pc = pix_cnt + 1'b1;
reg ce_x1, ce_x4, ce_x2;
reg ce_x4, ce_x2, ce_x1;
always @(negedge clk_sys) begin
reg old_ce;
reg old_ce, valid, hs;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
if(~&pix_len) pix_len <= pl;
if(~&pix_cnt) pix_cnt <= pc;
ce_x4 <= 0;
ce_x2 <= 0;
ce_x1 <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
ce_x4 <= 1;
end
if(pl == pixsz2) begin
ce_x2 <= 1;
end
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
if((pc == pixsz4) || (pc == pixsz2) || (pc == (pixsz2+pixsz4))) ce_x4 <= 1;
if( pc == pixsz2) ce_x2 <= 1;
old_ce <= ce_pix;
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
if(valid & ~hb_in & ~vb_in) begin
pixsz <= pl;
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
end
pix_len <= 0;
valid <= 1;
end
if(hb_in | vb_in) valid <= 0;
hs <= hs_out;
if((~hs & hs_out) || (pc >= pixsz)) begin
ce_x2 <= 1;
ce_x4 <= 1;
pix_len <= 0;
ce_x1 <= 1;
pix_cnt <= 0;
end
end
@ -102,88 +111,85 @@ Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
.inputpixel({b_d,g_d,r_d}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_frame(vb_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.hblank(hbo[0]&hbo[4]),
.hblank(hbo[0]&hbo[8]),
.outpixel({b_out,g_out,r_out})
);
reg [1:0] sd_line;
reg [2:0] vbo;
reg [6:0] hbo;
reg [DWIDTH:0] r_d;
reg [DWIDTH:0] g_d;
reg [DWIDTH:0] b_d;
reg [1:0] sd_line;
reg [3:0] vbo;
reg [3:0] vso;
reg [8:0] hbo;
reg req_line_reset;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg [11:0] hde_start, hde_end;
reg [31:0] hcnt;
reg [30:0] sd_hcnt;
reg [30:0] hs_start, hs_end;
reg [30:0] hde_start, hde_end;
reg hs, hs2, vs, hb;
reg hs, hb;
if(ce_x4) begin
hbo[8:1] <= hbo[7:0];
end
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
if(sd_hcnt == hde_start) begin
sd_hcnt <= 0;
vbo[3:1] <= vbo[2:0];
end
if(sd_hcnt == hs_end) begin
sd_line <= sd_line + 1'd1;
if(&vbo[3:2]) sd_line <= 1;
vso[3:1] <= vso[2:0];
end
if(sd_hcnt == hde_start)hbo[0] <= 0;
if(sd_hcnt == hde_end) hbo[0] <= 1;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_end) hs_out <= 0;
if(sd_hcnt == hs_start) hs_out <= 1;
hs <= hs_in;
hb <= hb_in;
if(ce_x1) begin
hs <= hs_in;
hb <= hb_in;
req_line_reset <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
if(hb && !hb_in) begin
hde_start <= {hcnt,1'b0};
vbo <= {vbo[1:0], vb_in};
end
if(!hb && hb_in) hde_end <= {hcnt,1'b0};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
vso <= (vso<<1) | vs_in;
hs_max <= {hcnt,1'b1};
hcnt <= 0;
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
hbo[6:1] <= hbo[5:0];
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
//prepare to read in advance
if(sd_hcnt == (hde_start-2)) begin
sd_line <= sd_line + 1'd1;
end
if(sd_hcnt == hde_start) hbo[0] <= 0;
if(sd_hcnt == hde_end) hbo[0] <= 1;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
hcnt <= hcnt + 1'd1;
if(hb && !hb_in) begin
hde_start <= hcnt[31:1];
hbo[0] <= 0;
hcnt <= 0;
sd_hcnt <= 0;
vbo <= {vbo[2:0],vb_in};
end
if(!hb && hb_in) hde_end <= hcnt[31:1];
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_end <= hcnt[31:1];
vso[0] <= vs_in;
end
// save position of rising edge
if(!hs && hs_in) hs_start <= hcnt[31:1];
end
endmodule

52
sys/scanlines.v Normal file
View File

@ -0,0 +1,52 @@
module scanlines #(parameter v2=0)
(
input clk,
input [1:0] scanlines,
input [23:0] din,
output reg [23:0] dout,
input hs,vs
);
reg [1:0] scanline;
always @(posedge clk) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) begin
if(v2) begin
scanline <= scanline + 1'd1;
if (scanline == scanlines) scanline <= 0;
end
else scanline <= scanline ^ scanlines;
end
if(old_vs && ~vs) scanline <= 0;
end
wire [7:0] r,g,b;
assign {r,g,b} = din;
always @(*) begin
case(scanline)
1: // reduce 25% = 1/2 + 1/4
dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
{1'b0, g[7:1]} + {2'b00, g[7:2]},
{1'b0, b[7:1]} + {2'b00, b[7:2]}};
2: // reduce 50% = 1/2
dout = {{1'b0, r[7:1]},
{1'b0, g[7:1]},
{1'b0, b[7:1]}};
3: // reduce 75% = 1/4
dout = {{2'b00, r[7:2]},
{2'b00, g[7:2]},
{2'b00, b[7:2]}};
default: dout = {r,g,b};
endcase
end
endmodule

126
sys/spdif.v
View File

@ -31,132 +31,6 @@
// altera message_off 10240
module spdif
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_RATE = 48000,
// Generated params
parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128),
parameter ERROR_BASE = 10000,
parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input half_rate,
// Output
output spdif_o,
// Audio interface (16-bit x 2 = RL)
input [15:0] audio_r,
input [15:0] audio_l,
output sample_req_o
);
reg lpf_ce;
always @(negedge clk_i) begin
reg [3:0] div;
div <= div + 1'd1;
if(div == 13) div <= 0;
lpf_ce <= !div;
end
wire [15:0] al, ar;
lpf48k #(15) lpf_l
(
.RESET(rst_i),
.CLK(clk_i),
.CE(lpf_ce),
.ENABLE(1),
.IDATA(audio_l),
.ODATA(al)
);
lpf48k #(15) lpf_r
(
.RESET(rst_i),
.CLK(clk_i),
.CE(lpf_ce),
.ENABLE(1),
.IDATA(audio_r),
.ODATA(ar)
);
reg bit_clk_q;
// Clock pulse generator
always @ (posedge rst_i or posedge clk_i) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg ce;
if (rst_i) begin
count_q <= 0;
error_q <= 0;
bit_clk_q <= 1;
ce <= 0;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
bit_clk_q <= 0;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) bit_clk_q <= 1;
end
end
end
//-----------------------------------------------------------------
// Core SPDIF
//-----------------------------------------------------------------
wire [31:0] sample_i = {ar, al};
spdif_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.bit_out_en_i(bit_clk_q),
.spdif_o(spdif_o),
.sample_i(sample_i),
.sample_req_o(sample_req_o)
);
endmodule
module spdif_core
(
input clk_i,
input rst_i,

78
sys/sync_vg.v
View File

@ -1,78 +0,0 @@
module sync_vg
#(
parameter X_BITS=12, Y_BITS=12
)
(
input wire clk,
input wire reset,
input wire [Y_BITS-1:0] v_total,
input wire [Y_BITS-1:0] v_fp,
input wire [Y_BITS-1:0] v_bp,
input wire [Y_BITS-1:0] v_sync,
input wire [X_BITS-1:0] h_total,
input wire [X_BITS-1:0] h_fp,
input wire [X_BITS-1:0] h_bp,
input wire [X_BITS-1:0] h_sync,
input wire [X_BITS-1:0] hv_offset,
output reg vs_out,
output reg hs_out,
output reg hde_out,
output reg vde_out,
output reg [Y_BITS-1:0] v_count_out,
output reg [X_BITS-1:0] h_count_out,
output reg [X_BITS-1:0] x_out,
output reg [Y_BITS-1:0] y_out
);
reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count;
/* horizontal counter */
always @(posedge clk)
if (reset)
h_count <= 0;
else
if (h_count < h_total - 1)
h_count <= h_count + 1'd1;
else
h_count <= 0;
/* vertical counter */
always @(posedge clk)
if (reset)
v_count <= 0;
else
if (h_count == h_total - 1)
begin
if (v_count == v_total - 1)
v_count <= 0;
else
v_count <= v_count + 1'd1;
end
always @(posedge clk)
if (reset)
{ vs_out, hs_out, hde_out, vde_out } <= 0;
else begin
hs_out <= ((h_count < h_sync));
hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1);
vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1);
if ((v_count == 0) && (h_count == hv_offset))
vs_out <= 1'b1;
else if ((v_count == v_sync) && (h_count == hv_offset))
vs_out <= 1'b0;
/* H_COUNT_OUT and V_COUNT_OUT */
h_count_out <= h_count;
v_count_out <= v_count;
/* X and Y coords for a backend pattern generator */
x_out <= h_count - (h_sync + h_bp);
y_out <= v_count - (v_sync + v_bp);
end
endmodule

50
sys/sys.qip
View File

@ -1,24 +1,26 @@
set_global_assignment -name VERILOG_FILE sys/sys_top.v
set_global_assignment -name SDC_FILE sys/sys_top.sdc
set_global_assignment -name QIP_FILE sys/pll.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
set_global_assignment -name VERILOG_FILE sys/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
set_global_assignment -name VERILOG_FILE sys/osd.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv
set_global_assignment -name VERILOG_FILE sys/sync_vg.v
set_global_assignment -name VERILOG_FILE sys/pattern_vg.v
set_global_assignment -name VERILOG_FILE sys/i2c.v
set_global_assignment -name VERILOG_FILE sys/i2s.v
set_global_assignment -name VERILOG_FILE sys/spdif.v
set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
set_global_assignment -name VERILOG_FILE sys/sd_card.v
set_global_assignment -name VERILOG_FILE sys/hps_io.v
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart

30
sys/sys_q13.qip Normal file
View File

@ -0,0 +1,30 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll/pll_0002.v ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll/pll_0002.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart

24
sys/sys_top.sdc
View File

@ -3,43 +3,29 @@ create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
create_clock -period 10.0 [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
derive_pll_clocks
# Specify PLL-generated clock(s)
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
-to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-setup 2
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}]
# Put constraints on input ports
set_false_path -from [get_ports {KEY*}] -to *
set_false_path -from [get_ports {BTN_*}] -to *

1941
sys/sys_top.v
View File

File diff suppressed because it is too large Load Diff

948
sys/sysmem.sv
View File

@ -1,531 +1,429 @@
`timescale 1 ps / 1 ps
module sysmem_lite
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
output ctl_clock,
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req, // .warm_req
input vbuf_clk, // vbuf.clk
input [27:0] vbuf_address, // vbuf.address
input [7:0] vbuf_burstcount, // .burstcount
output vbuf_waitrequest, // .waitrequest
output [127:0] vbuf_readdata, // .readdata
output vbuf_readdatavalid, // .readdatavalid
input vbuf_read, // .read
input [127:0] vbuf_writedata, // .writedata
input [15:0] vbuf_byteenable, // .byteenable
input vbuf_write // .write
);
assign ctl_clock = clk_vip_clk;
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
wire clk_vip_clk;
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (vbuf_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (vbuf_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (vbuf_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (vbuf_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (vbuf_readdata), // .readdata
.f2h_sdram0_READDATAVALID (vbuf_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (vbuf_read), // .read
.f2h_sdram0_WRITEDATA (vbuf_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (vbuf_byteenable), // .byteenable
.f2h_sdram0_WRITE (vbuf_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.reset_vip (0), // .reset_vip
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule
`timescale 1 ps / 1 ps
module sysmem
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
module sysmem_lite
(
output clock,
output reset_out,
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
input reset_hps_cold_req,
input reset_hps_warm_req,
input reset_core_req,
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req, // .warm_req
input ram1_clk,
input [28:0] ram1_address,
input [7:0] ram1_burstcount,
output ram1_waitrequest,
output [63:0] ram1_readdata,
output ram1_readdatavalid,
input ram1_read,
input [63:0] ram1_writedata,
input [7:0] ram1_byteenable,
input ram1_write,
input [27:0] ram_vip_address, // ram_vip.address
input [7:0] ram_vip_burstcount, // .burstcount
output ram_vip_waitrequest, // .waitrequest
output [127:0] ram_vip_readdata, // .readdata
output ram_vip_readdatavalid, // .readdatavalid
input ram_vip_read, // .read
input [127:0] ram_vip_writedata, // .writedata
input [15:0] ram_vip_byteenable, // .byteenable
input ram_vip_write, // .write
input ram2_clk,
input [28:0] ram2_address,
input [7:0] ram2_burstcount,
output ram2_waitrequest,
output [63:0] ram2_readdata,
output ram2_readdatavalid,
input ram2_read,
input [63:0] ram2_writedata,
input [7:0] ram2_byteenable,
input ram2_write,
input vbuf_clk,
input [27:0] vbuf_address,
input [7:0] vbuf_burstcount,
output vbuf_waitrequest,
output [127:0] vbuf_readdata,
output vbuf_readdatavalid,
input vbuf_read,
input [127:0] vbuf_writedata,
input [15:0] vbuf_byteenable,
input vbuf_write
);
assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req;
output clk_vip_clk, // clk_vip.clk
output reset_vip_reset // reset_vip.reset
);
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (ram_vip_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (ram_vip_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (ram_vip_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (ram_vip_readdata), // .readdata
.f2h_sdram0_READDATAVALID (ram_vip_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (ram_vip_read), // .read
.f2h_sdram0_WRITEDATA (ram_vip_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (ram_vip_byteenable), // .byteenable
.f2h_sdram0_WRITE (ram_vip_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (reset_vip_reset), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule
module sysmem_HPS_fpga_interfaces
(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_cold_reset_req
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
// f2h_warm_reset_req
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
// h2f_user0_clock
,output wire [1 - 1 : 0 ] h2f_user0_clk
// f2h_sdram0_data
,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
// f2h_sdram0_clock
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
// f2h_sdram1_data
,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram1_READ
,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
// f2h_sdram1_clock
,input wire [1 - 1 : 0 ] f2h_sdram1_clk
// f2h_sdram2_data
,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram2_READ
,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
// f2h_sdram2_clock
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
);
wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_warm_rst_req_n({
f2h_warm_rst_req_n[0:0] // 0:0
})
,.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
f2h_cold_rst_req_n[0:0] // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_rfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.cfg_wfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.rd_ready_3({
1'b1 // 0:0
})
,.cmd_port_clk_2({
intermediate[28:28] // 0:0
})
,.rd_ready_2({
1'b1 // 0:0
})
,.cmd_port_clk_1({
intermediate[19:19] // 0:0
})
,.rd_ready_1({
1'b1 // 0:0
})
,.cmd_port_clk_0({
intermediate[10:10] // 0:0
})
,.rd_ready_0({
1'b1 // 0:0
})
,.wrack_ready_2({
1'b1 // 0:0
})
,.wrack_ready_1({
1'b1 // 0:0
})
,.wrack_ready_0({
1'b1 // 0:0
})
,.cmd_ready_2({
intermediate[21:21] // 0:0
})
,.cmd_ready_1({
intermediate[12:12] // 0:0
})
,.cmd_ready_0({
intermediate[1:1] // 0:0
})
,.cfg_port_width({
12'b000000010110 // 11:0
})
,.rd_valid_3({
f2h_sdram2_READDATAVALID[0:0] // 0:0
})
,.rd_valid_2({
f2h_sdram1_READDATAVALID[0:0] // 0:0
})
,.rd_valid_1({
f2h_sdram0_READDATAVALID[0:0] // 0:0
})
,.rd_clk_3({
intermediate[22:22] // 0:0
})
,.rd_data_3({
f2h_sdram2_READDATA[63:0] // 63:0
})
,.rd_clk_2({
intermediate[13:13] // 0:0
})
,.rd_data_2({
f2h_sdram1_READDATA[63:0] // 63:0
})
,.rd_clk_1({
intermediate[3:3] // 0:0
})
,.rd_data_1({
f2h_sdram0_READDATA[127:64] // 63:0
})
,.rd_clk_0({
intermediate[2:2] // 0:0
})
,.rd_data_0({
f2h_sdram0_READDATA[63:0] // 63:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cmd_valid_2({
intermediate[26:26] // 0:0
})
,.cmd_valid_1({
intermediate[17:17] // 0:0
})
,.cmd_valid_0({
intermediate[8:8] // 0:0
})
,.cfg_cport_rfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_data_3({
2'b00 // 89:88
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram2_WRITEDATA[63:0] // 63:0
})
,.wr_data_2({
2'b00 // 89:88
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram1_WRITEDATA[63:0] // 63:0
})
,.wr_data_1({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[127:64] // 63:0
})
,.cfg_cport_type({
12'b000000111111 // 11:0
})
,.wr_data_0({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[63:0] // 63:0
})
,.cfg_cport_wfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_clk_3({
intermediate[24:24] // 0:0
})
,.wr_clk_2({
intermediate[15:15] // 0:0
})
,.wr_clk_1({
intermediate[6:6] // 0:0
})
,.wr_clk_0({
intermediate[5:5] // 0:0
})
,.cmd_data_2({
18'b000000000000000000 // 59:42
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram2_ADDRESS[28:0] // 30:2
,intermediate[25:25] // 1:1
,intermediate[23:23] // 0:0
})
,.cmd_data_1({
18'b000000000000000000 // 59:42
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram1_ADDRESS[28:0] // 30:2
,intermediate[16:16] // 1:1
,intermediate[14:14] // 0:0
})
,.cmd_data_0({
18'b000000000000000000 // 59:42
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
,4'b0000 // 33:30
,f2h_sdram0_ADDRESS[27:0] // 29:2
,intermediate[7:7] // 1:1
,intermediate[4:4] // 0:0
})
);
endmodule
.f2h_cold_rst_req_n (~reset_hps_cold_req),
.f2h_warm_rst_req_n (~reset_hps_warm_req),
.h2f_user0_clk (clock),
.h2f_rst_n (hps_h2f_reset_n),
.f2h_sdram0_clk (vbuf_clk),
.f2h_sdram0_ADDRESS (vbuf_address),
.f2h_sdram0_BURSTCOUNT (vbuf_burstcount),
.f2h_sdram0_WAITREQUEST (vbuf_waitrequest),
.f2h_sdram0_READDATA (vbuf_readdata),
.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),
.f2h_sdram0_READ (vbuf_read),
.f2h_sdram0_WRITEDATA (vbuf_writedata),
.f2h_sdram0_BYTEENABLE (vbuf_byteenable),
.f2h_sdram0_WRITE (vbuf_write),
.f2h_sdram1_clk (ram1_clk),
.f2h_sdram1_ADDRESS (ram1_address),
.f2h_sdram1_BURSTCOUNT (ram1_burstcount),
.f2h_sdram1_WAITREQUEST (ram1_waitrequest),
.f2h_sdram1_READDATA (ram1_readdata),
.f2h_sdram1_READDATAVALID (ram1_readdatavalid),
.f2h_sdram1_READ (ram1_read),
.f2h_sdram1_WRITEDATA (ram1_writedata),
.f2h_sdram1_BYTEENABLE (ram1_byteenable),
.f2h_sdram1_WRITE (ram1_write),
.f2h_sdram2_clk (ram2_clk),
.f2h_sdram2_ADDRESS (ram2_address),
.f2h_sdram2_BURSTCOUNT (ram2_burstcount),
.f2h_sdram2_WAITREQUEST (ram2_waitrequest),
.f2h_sdram2_READDATA (ram2_readdata),
.f2h_sdram2_READDATAVALID (ram2_readdatavalid),
.f2h_sdram2_READ (ram2_read),
.f2h_sdram2_WRITEDATA (ram2_writedata),
.f2h_sdram2_BYTEENABLE (ram2_byteenable),
.f2h_sdram2_WRITE (ram2_write)
);
wire hps_h2f_reset_n;
reg init_reset_n = 0;
always @(posedge clock) begin
integer timeout = 0;
if(timeout < 2000000) begin
init_reset_n <= 0;
timeout <= timeout + 1;
end
else init_reset_n <= 1;
end
endmodule
module sysmem_HPS_fpga_interfaces
(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_cold_reset_req
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
// f2h_warm_reset_req
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
// h2f_user0_clock
,output wire [1 - 1 : 0 ] h2f_user0_clk
// f2h_sdram0_data
,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
// f2h_sdram0_clock
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
// f2h_sdram1_data
,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram1_READ
,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
// f2h_sdram1_clock
,input wire [1 - 1 : 0 ] f2h_sdram1_clk
// f2h_sdram2_data
,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram2_READ
,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
// f2h_sdram2_clock
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
);
wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_warm_rst_req_n({
f2h_warm_rst_req_n[0:0] // 0:0
})
,.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
f2h_cold_rst_req_n[0:0] // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_rfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.cfg_wfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.rd_ready_3({
1'b1 // 0:0
})
,.cmd_port_clk_2({
intermediate[28:28] // 0:0
})
,.rd_ready_2({
1'b1 // 0:0
})
,.cmd_port_clk_1({
intermediate[19:19] // 0:0
})
,.rd_ready_1({
1'b1 // 0:0
})
,.cmd_port_clk_0({
intermediate[10:10] // 0:0
})
,.rd_ready_0({
1'b1 // 0:0
})
,.wrack_ready_2({
1'b1 // 0:0
})
,.wrack_ready_1({
1'b1 // 0:0
})
,.wrack_ready_0({
1'b1 // 0:0
})
,.cmd_ready_2({
intermediate[21:21] // 0:0
})
,.cmd_ready_1({
intermediate[12:12] // 0:0
})
,.cmd_ready_0({
intermediate[1:1] // 0:0
})
,.cfg_port_width({
12'b000000010110 // 11:0
})
,.rd_valid_3({
f2h_sdram2_READDATAVALID[0:0] // 0:0
})
,.rd_valid_2({
f2h_sdram1_READDATAVALID[0:0] // 0:0
})
,.rd_valid_1({
f2h_sdram0_READDATAVALID[0:0] // 0:0
})
,.rd_clk_3({
intermediate[22:22] // 0:0
})
,.rd_data_3({
f2h_sdram2_READDATA[63:0] // 63:0
})
,.rd_clk_2({
intermediate[13:13] // 0:0
})
,.rd_data_2({
f2h_sdram1_READDATA[63:0] // 63:0
})
,.rd_clk_1({
intermediate[3:3] // 0:0
})
,.rd_data_1({
f2h_sdram0_READDATA[127:64] // 63:0
})
,.rd_clk_0({
intermediate[2:2] // 0:0
})
,.rd_data_0({
f2h_sdram0_READDATA[63:0] // 63:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cmd_valid_2({
intermediate[26:26] // 0:0
})
,.cmd_valid_1({
intermediate[17:17] // 0:0
})
,.cmd_valid_0({
intermediate[8:8] // 0:0
})
,.cfg_cport_rfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_data_3({
2'b00 // 89:88
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram2_WRITEDATA[63:0] // 63:0
})
,.wr_data_2({
2'b00 // 89:88
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram1_WRITEDATA[63:0] // 63:0
})
,.wr_data_1({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[127:64] // 63:0
})
,.cfg_cport_type({
12'b000000111111 // 11:0
})
,.wr_data_0({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[63:0] // 63:0
})
,.cfg_cport_wfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_clk_3({
intermediate[24:24] // 0:0
})
,.wr_clk_2({
intermediate[15:15] // 0:0
})
,.wr_clk_1({
intermediate[6:6] // 0:0
})
,.wr_clk_0({
intermediate[5:5] // 0:0
})
,.cmd_data_2({
18'b000000000000000000 // 59:42
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram2_ADDRESS[28:0] // 30:2
,intermediate[25:25] // 1:1
,intermediate[23:23] // 0:0
})
,.cmd_data_1({
18'b000000000000000000 // 59:42
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram1_ADDRESS[28:0] // 30:2
,intermediate[16:16] // 1:1
,intermediate[14:14] // 0:0
})
,.cmd_data_0({
18'b000000000000000000 // 59:42
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
,4'b0000 // 33:30
,f2h_sdram0_ADDRESS[27:0] // 29:2
,intermediate[7:7] // 1:1
,intermediate[4:4] // 0:0
})
);
endmodule

91
sys/video_cleaner.sv Normal file
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@ -0,0 +1,91 @@
//
//
// Copyright (c) 2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module video_cleaner
(
input clk_vid,
input ce_pix,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output VGA_DE,
// optional aligned blank
output reg HBlank_out,
output reg VBlank_out
);
wire hs, vs;
s_fix sync_v(clk_vid, HSync, hs);
s_fix sync_h(clk_vid, VSync, vs);
wire hbl = hs | HBlank;
wire vbl = vs | VBlank;
assign VGA_DE = ~(HBlank_out | VBlank_out);
always @(posedge clk_vid) begin
if(ce_pix) begin
HBlank_out <= hbl;
VGA_VS <= vs;
VGA_HS <= hs;
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end
end
endmodule
module s_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule

1177
sys/vip.qsys
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159
sys/vip_config.sv
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@ -1,159 +0,0 @@
module vip_config
(
input clk,
input reset,
input [7:0] ARX,
input [7:0] ARY,
input CFG_SET,
input [11:0] WIDTH,
input [11:0] HFP,
input [11:0] HBP,
input [11:0] HS,
input [11:0] HEIGHT,
input [11:0] VFP,
input [11:0] VBP,
input [11:0] VS,
input [11:0] VSET,
output reg [8:0] address,
output reg write,
output reg [31:0] writedata,
input waitrequest
);
reg newres = 1;
wire [21:0] init[23] =
'{
//video mode
{newres, 2'd2, 7'd04, 12'd0 }, //Bank
{newres, 2'd2, 7'd30, 12'd0 }, //Valid
{newres, 2'd2, 7'd05, 12'd0 }, //Progressive/Interlaced
{newres, 2'd2, 7'd06, w }, //Active pixel count
{newres, 2'd2, 7'd07, h }, //Active line count
{newres, 2'd2, 7'd09, hfp }, //Horizontal Front Porch
{newres, 2'd2, 7'd10, hs }, //Horizontal Sync Length
{newres, 2'd2, 7'd11, hb }, //Horizontal Blanking (HFP+HBP+HSync)
{newres, 2'd2, 7'd12, vfp }, //Vertical Front Porch
{newres, 2'd2, 7'd13, vs }, //Vertical Sync Length
{newres, 2'd2, 7'd14, vb }, //Vertical blanking (VFP+VBP+VSync)
{newres, 2'd2, 7'd30, 12'd1 }, //Valid
{newres, 2'd2, 7'd00, 12'd1 }, //Go
//mixer
{ 1'd1, 2'd1, 7'd03, w }, //Bkg Width
{ 1'd1, 2'd1, 7'd04, h }, //Bkg Height
{ 1'd1, 2'd1, 7'd08, posx }, //Pos X
{ 1'd1, 2'd1, 7'd09, posy }, //Pos Y
{ 1'd1, 2'd1, 7'd10, 12'd1 }, //Enable Video 0
{ 1'd1, 2'd1, 7'd00, 12'd1 }, //Go
//scaler
{ 1'd1, 2'd0, 7'd03, videow }, //Output Width
{ 1'd1, 2'd0, 7'd04, videoh }, //Output Height
{ 1'd1, 2'd0, 7'd00, 12'd1 }, //Go
22'h3FFFFF
};
reg [11:0] w;
reg [11:0] hfp;
reg [11:0] hbp;
reg [11:0] hs;
reg [11:0] hb;
reg [11:0] h;
reg [11:0] vfp;
reg [11:0] vbp;
reg [11:0] vs;
reg [11:0] vb;
reg [11:0] videow;
reg [11:0] videoh;
reg [11:0] posx;
reg [11:0] posy;
always @(posedge clk) begin
reg [7:0] state = 0;
reg [7:0] arx, ary;
reg [7:0] arxd, aryd;
reg [11:0] vset, vsetd;
reg cfg, cfgd;
reg [31:0] wcalc;
reg [31:0] hcalc;
reg [12:0] timeout = 0;
arxd <= ARX;
aryd <= ARY;
vsetd <= VSET;
cfg <= CFG_SET;
cfgd <= cfg;
write <= 0;
if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin
arx <= arxd;
ary <= aryd;
vset <= vsetd;
timeout <= '1;
state <= 0;
if(reset || (~cfgd && cfg)) newres <= 1;
end
else
if(timeout > 0)
begin
timeout <= timeout - 1'd1;
state <= 1;
if(!(timeout & 'h1f)) case(timeout>>5)
5: begin
w <= WIDTH;
hfp <= HFP;
hbp <= HBP;
hs <= HS;
h <= HEIGHT;
vfp <= VFP;
vbp <= VBP;
vs <= VS;
end
4: begin
hb <= hfp+hbp+hs;
vb <= vfp+vbp+vs;
end
3: begin
wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary;
hcalc <= (w*ary)/arx;
end
2: begin
videow <= (!vset && (wcalc > w)) ? w : wcalc[11:0];
videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0];
end
1: begin
posx <= (w - videow)>>1;
posy <= (h - videoh)>>1;
end
endcase
end
else
if(~waitrequest && state)
begin
state <= state + 1'd1;
write <= 0;
if((state&3)==3) begin
if(init[state>>2] == 22'h3FFFFF) begin
state <= 0;
newres <= 0;
end
else begin
writedata <= 0;
{write, address, writedata[11:0]} <= init[state>>2];
end
end
end
end
endmodule